rewrite entire test harness

1 files changed, 4 insertions, 4 deletions

diff --git a/spi_master.v b/spi_master.v
index cc5f01d..ae75394 100644
--- a/spi_master.v
+++ b/spi_master.v
@@ -31,10 +31,10 @@ spi_master
 `endif
 `ifndef SPI_MASTER_NO_WRITE
 	input [WID-1:0] to_slave,
-	output mosi,
+	output reg mosi,
 `endif
-	output sck_wire,
-	output finished,
+	output reg sck_wire,
+	output reg finished,
 	input arm
 );
 
@@ -141,7 +141,7 @@ always @ (posedge clk) begin
 			timer <= 0;
 			// Stop transfer when the clock returns
 			// to its original polarity.
-			if (bit_counter == WID && sck == POLARITY) begin
+			if (bit_counter == WID[WID_LEN-1:0] && sck == POLARITY[0]) begin
 				state <= WAIT_FINISHED;
 			end else begin
 				state <= ON_CYCLE;