mode 00, write from master to slave works

1 files changed, 21 insertions, 5 deletions

diff --git a/spi_master.v b/spi_master.v
index 7bb8db1..baf2f5e 100644
--- a/spi_master.v
+++ b/spi_master.v
@@ -72,8 +72,22 @@ always @ (posedge clk) begin
 			idle_state();
 			finished <= 0;
 		end else begin
-			state <= ON_CYCLE;
-			send_buf <= to_slave;
+			/* at Mode 00, the transmission starts with
+			 * a rising edge, and at mode 11, it starts
+			 * with a falling edge. For both modes,
+			 * these are READs.
+			 *
+			 * For mode 01 and mode 10, the first
+			 * action is a WRITE.
+			 */
+			if (POLARITY == PHASE) begin
+				mosi <= to_slave[WID-1];
+				send_buf <= to_slave << 1;
+				state <= CYCLE_WAIT;
+			end else begin
+				send_buf <= to_slave;
+				state <= ON_CYCLE;
+			end
 		end
 	end
 	ON_CYCLE: begin
@@ -84,7 +98,7 @@ always @ (posedge clk) begin
 				read_data();
 			end
 
-			if (POLARITY == 1) begin
+			if (POLARITY == 0) begin
 				bit_counter <= bit_counter + 1;
 			end
 		end else begin // falling edge
@@ -94,7 +108,7 @@ always @ (posedge clk) begin
 				write_data();
 			end
 
-			if (POLARITY == 0) begin
+			if (POLARITY == 1) begin
 				bit_counter <= bit_counter + 1;
 			end
 		end
@@ -103,7 +117,9 @@ always @ (posedge clk) begin
 	CYCLE_WAIT: begin
 		if (timer == CYCLE_HALF_WAIT) begin
 			timer <= 0;
-			if (bit_counter == WID) begin
+			// Stop transfer when the clock returns
+			// to its original polarity.
+			if (bit_counter == WID && sck == POLARITY) begin
 				state <= WAIT_FINISHED;
 			end else begin
 				state <= ON_CYCLE;