diff options
| author | 2022-10-23 04:27:28 -0400 | |
|---|---|---|
| committer | 2022-10-23 04:27:28 -0400 | |
| commit | fe1139e02e247c023bc594376117220fe35d180c (patch) | |
| tree | 4b936c8a712603feb740af24006f51c8f78fda8d /spi_master.v | |
| parent | bump version (diff) | |
add SS
Diffstat (limited to 'spi_master.v')
| -rw-r--r-- | spi_master.v | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/spi_master.v b/spi_master.v index 053686f..d8b9020 100644 --- a/spi_master.v +++ b/spi_master.v @@ -18,7 +18,9 @@ spi_master #( parameter WID = 24, // Width of bits per transaction. parameter WID_LEN = 5, // Length in bits required to store WID - parameter CYCLE_HALF_WAIT = 1, // Half of the wait time of a cycle + parameter CYCLE_HALF_WAIT = 1, // One less than half of the wait time of a cycle. + // One cycle of a transfer is 2(CYCLE_HALF_WAIT + 1) + // clock cycles. parameter TIMER_LEN = 3, // Length in bits required to store CYCLE_HALF_WAIT parameter POLARITY = 0, // 0 = sck idle low, 1 = sck idle high parameter PHASE = 0 // 0 = rising-read falling-write, 1 = rising-write falling-read. @@ -134,6 +136,7 @@ always @ (posedge clk) begin bit_counter <= bit_counter + 1; end end + state <= CYCLE_WAIT; end CYCLE_WAIT: begin |
