diff options
| author |  Peter McGoron
| 2023-04-20 19:10:04 +0000 |
|---|---|---|
| committer | Peter McGoron
| 2023-04-20 19:10:04 +0000 |
| commit | 1c6672e618e901c2933cf9e81d97471f4ef560d3 (patch) | |
| tree | ffba660091a7ab1a494bddcf8a6b9618e554f5e5 /spi_master_ss_template.v | |
| parent | add ready_to_arm to indiciate when the module can accept another command (diff) | |
add reset pin
Diffstat (limited to 'spi_master_ss_template.v')
| -rw-r--r-- | spi_master_ss_template.v | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/spi_master_ss_template.v b/spi_master_ss_template.v index f231f70..6e4b970 100644 --- a/spi_master_ss_template.v +++ b/spi_master_ss_template.v @@ -17,6 +17,7 @@ module `SPI_MASTER_SS_NAME ) ( input clk, + input rst_L, `ifndef SPI_MASTER_NO_READ output [WID-1:0] from_slave, input miso, @@ -45,6 +46,7 @@ assign ss_L = !ss; .PHASE(PHASE) ) master ( .clk(clk), + .rst_L(rst_L), `ifndef SPI_MASTER_NO_READ .from_slave(from_slave), .miso(miso), @@ -72,7 +74,12 @@ task master_arm(); endtask always @ (posedge clk) begin - case (state) + if (!rst_L) begin + state <= WAIT_ON_ARM; + timer <= 0; + arm_master <= 0; + ss <= 0; + end else case (state) WAIT_ON_ARM: begin if (arm) begin timer <= 1; |