start cleanup of SPI

1 files changed, 20 insertions, 17 deletions

diff --git a/spi_master_ss_template.v b/spi_master_ss_template.v
index fff9d08..e5624ce 100644
--- a/spi_master_ss_template.v
+++ b/spi_master_ss_template.v
@@ -1,36 +1,39 @@
-/* (c) Peter McGoron 2022 v0.3
+/* (c) Peter McGoron 2022 v0.4
  * This Source Code Form is subject to the terms of the Mozilla Public
  * License, v.2.0. If a copy of the MPL was not distributed with this
  * file, You can obtain one at https://mozilla.org/MPL/2.0/.
  */
+
 /* spi master with integrated ability to wait a certain amount of cycles
  * after activating SS.
  */
 
-module `SPI_MASTER_SS_NAME
+module spi_master_ss
 #(
+	parameter SS_WAIT = 1, /* Amount of cycles to wait for SS
+	                          to enable */
+	parameter SS_WAIT_TIMER_LEN = 2, /* Amount of bits required to
+	                                    store the SS wait time */
+
+	parameter ENABLE_MISO = 1,
+	parameter ENABLE_MOSI = 1,
 	parameter WID = 24,
 	parameter WID_LEN = 5,
 	parameter CYCLE_HALF_WAIT = 1,
 	parameter TIMER_LEN = 3,
 
-	parameter SS_WAIT = 1,
-	parameter SS_WAIT_TIMER_LEN = 2,
-
 	parameter POLARITY = 0,
 	parameter PHASE = 0
-)
-(
+) (
 	input clk,
 	input rst_L,
-`ifndef SPI_MASTER_NO_READ
+
 	output [WID-1:0] from_slave,
 	input miso,
-`endif
-`ifndef SPI_MASTER_NO_WRITE
+
 	input [WID-1:0] to_slave,
 	output reg mosi,
-`endif
+
 	output sck_wire,
 	output finished,
 	output ready_to_arm,
@@ -42,7 +45,9 @@ reg ss = 0;
 reg arm_master = 0;
 assign ss_L = !ss;
 
-`SPI_MASTER_NAME #(
+spi_master #(
+	.ENABLE_MISO(ENABLE_MISO),
+	.ENABLE_MOSI(ENABLE_MOSI),
 	.WID(WID),
 	.WID_LEN(WID_LEN),
 	.CYCLE_HALF_WAIT(CYCLE_HALF_WAIT),
@@ -52,14 +57,13 @@ assign ss_L = !ss;
 ) master (
 	.clk(clk),
 	.rst_L(rst_L),
-`ifndef SPI_MASTER_NO_READ
+
 	.from_slave(from_slave),
 	.miso(miso),
-`endif
-`ifndef SPI_MASTER_NO_WRITE
+
 	.to_slave(to_slave),
 	.mosi(mosi),
-`endif
+
 	.sck_wire(sck_wire),
 	.finished(finished),
 	.ready_to_arm(ready_to_arm),
@@ -120,4 +124,3 @@ always @ (posedge clk) begin
 end
 
 endmodule
-`undefineall