cleanup, add ready pin to slave

1 files changed, 18 insertions, 12 deletions

diff --git a/spi_slave.v b/spi_slave.v
index 8efce47..54a5051 100644
--- a/spi_slave.v
+++ b/spi_slave.v
@@ -18,6 +18,7 @@ module spi_slave
 	output miso,
 `endif
 	output finished,
+	input rdy,
 	output err
 );
 
@@ -25,6 +26,7 @@ wire ss = !ss_L;
 reg sck_delay = 0;
 reg [WID_LEN-1:0] bit_counter = 0;
 reg ss_delay = 0;
+reg ready_at_start = 0;
 
 `ifndef SPI_SLAVE_NO_WRITE
 reg [WID-1:0] send_buf = 0;
@@ -59,6 +61,14 @@ task setup_bits();
 	end
 endtask
 
+task check_counter();
+	if (bit_counter == WID) begin
+		err <= ready_at_start;
+	end else begin
+		bit_counter <= bit_counter + 1;
+	end
+endtask
+
 always @ (posedge clk) begin
 	sck_delay <= sck;
 	ss_delay <= ss;
@@ -68,11 +78,12 @@ always @ (posedge clk) begin
 		bit_counter <= 0;
 		finished <= 0;
 		err <= 0;
+		ready_at_start <= rdy;
 
 		setup_bits();
 	end
 	2'b10: begin // falling edge
-		finished <= 1;
+		finished <= ready_at_start;
 	end
 	2'b11: begin
 		case ({sck_delay, sck})
@@ -84,11 +95,7 @@ always @ (posedge clk) begin
 			end
 
 			if (POLARITY == 0) begin
-				if (bit_counter == WID) begin
-					err <= 1;
-				end else begin
-					bit_counter <= bit_counter + 1;
-				end
+				check_counter();
 			end
 		end
 		2'b10: begin // falling edge
@@ -99,17 +106,16 @@ always @ (posedge clk) begin
 			end
 
 			if (POLARITY == 1) begin
-				if (bit_counter == WID) begin
-					err <= 1;
-				end else begin
-					bit_counter <= bit_counter + 1;
-				end
+				check_counter();
 			end
 		end
 		default: ;
 		endcase
 	end
-	2'b00: ;
+	2'b00: if (!rdy) begin
+		finished <= 0;
+		err <= 0;
+	end
 	endcase
 end