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| author |  Peter McGoron
| 2023-04-20 19:10:04 +0000 |
|---|---|---|
| committer | Peter McGoron
| 2023-04-20 19:10:04 +0000 |
| commit | 1c6672e618e901c2933cf9e81d97471f4ef560d3 (patch) | |
| tree | ffba660091a7ab1a494bddcf8a6b9618e554f5e5 /tests/simtop.v | |
| parent | add ready_to_arm to indiciate when the module can accept another command (diff) | |
add reset pin
Diffstat (limited to '')
| -rw-r--r-- | tests/simtop.v | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/tests/simtop.v b/tests/simtop.v index 71981a8..1e6662a 100644 --- a/tests/simtop.v +++ b/tests/simtop.v @@ -12,6 +12,7 @@ module simtop parameter WID_LEN = 5 ) ( input clk, + input rst_L, `ifndef SPI_MASTER_NO_WRITE input [WID-1:0] master_to_slave, output [WID-1:0] from_master, @@ -62,6 +63,7 @@ reg slave_error; .WID_LEN(WID_LEN) ) master ( .clk(clk), + .rst_L(rst_L), `ifndef SPI_MASTER_NO_WRITE .to_slave(master_to_slave), .mosi(mosi), @@ -86,6 +88,7 @@ reg slave_error; .WID_LEN(WID_LEN) ) slave ( .clk(clk), + .rst_L(rst_L), .sck(sck), .ss_L(ss_L), `ifndef SPI_MASTER_NO_WRITE |