add ready_to_arm to indiciate when the module can accept another command

1 files changed, 4 insertions, 2 deletions

diff --git a/tests/simtop.v b/tests/simtop.v
index a1461bc..71981a8 100644
--- a/tests/simtop.v
+++ b/tests/simtop.v
@@ -26,6 +26,7 @@ module simtop
 `endif
 	input rdy,
 	output master_finished,
+	output ready_to_arm,
 	output err
 );
 
@@ -74,6 +75,7 @@ reg slave_error;
 `endif
 	.sck_wire(sck),
 	.finished(master_finished),
+	.ready_to_arm(ready_to_arm),
 	.arm(activate)
 );
 
@@ -99,11 +101,11 @@ reg slave_error;
 	.err(err)
 );
 
-/*
+`ifdef SIMULATION
 initial begin
 	$dumpfile(`VCDFILE);
 	$dumpvars;
 end
-*/
+`endif
 
 endmodule