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| author | 2022-07-21 02:37:22 -0400 | |
|---|---|---|
| committer | 2022-07-21 02:37:22 -0400 | |
| commit | 4a683b8f654f3ecb6f2408dad3a9cfa60f3b39e6 (patch) | |
| tree | a6c324803c18ad9a6dbcd65d54b80984d39f58d0 /tests/spi_write_read.v | |
| parent | cleanup, add ready pin to slave (diff) | |
move tests
Diffstat (limited to '')
| -rw-r--r-- | tests/spi_write_read.v (renamed from test_spi_write_read_mode0.v) | 23 |
1 files changed, 14 insertions, 9 deletions
diff --git a/test_spi_write_read_mode0.v b/tests/spi_write_read.v index 554b92e..8045a1c 100644 --- a/test_spi_write_read_mode0.v +++ b/tests/spi_write_read.v @@ -1,13 +1,21 @@ -module test_spi_write_read_mode0 +/* (c) Peter McGoron 2022 + * This Source Code Form is subject to the terms of the Mozilla Public + * License, v.2.0. If a copy of the MPL was not distributed with this + * file, You can obtain one at https://mozilla.org/MPL/2.0/. + */ + +module spi_write_read +#( + parameter POLARITY = 0, + parameter PHASE = 0 +) ( input clk, input [23:0] data_ctrl, input activate, input ss, input rdy, - output master_finished, - output slave_finished, - output slave_error + output master_finished ); wire miso; @@ -16,6 +24,8 @@ wire sck; wire ss_L = !ss; reg [23:0] from_slave_data; +reg slave_finished; +reg slave_error; spi_master master ( @@ -52,9 +62,4 @@ always @ (posedge clk) begin end end -initial begin - $dumpfile("test_spi_write_read_mode0.vcd"); - $dumpvars(); -end - endmodule |
