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authorGravatar Peter McGoron 2022-10-23 12:37:07 -0400
committerGravatar Peter McGoron 2022-10-23 12:37:07 -0400
commit039507d13ab003ad432eb903224dcf7242cc9c23 (patch)
tree45da3812a0fdc61a586ae22057f2fe02a0fb7893 /tests/write_read.cpp
parentfactor out code (diff)
test master with SS
Diffstat (limited to 'tests/write_read.cpp')
-rw-r--r--tests/write_read.cpp15
1 files changed, 12 insertions, 3 deletions
diff --git a/tests/write_read.cpp b/tests/write_read.cpp
index 2394b63..387b58a 100644
--- a/tests/write_read.cpp
+++ b/tests/write_read.cpp
@@ -4,6 +4,12 @@
Vsimtop *sim;
+#ifdef SPI_MASTER_SS
+# define SET_SS(mod, v)
+#else
+# define SET_SS(mod,v) ((mod)->ss = (v))
+#endif
+
uint32_t main_time = 0;
double sc_time_stamp() {
@@ -33,7 +39,7 @@ static void test_cross_transfer(unsigned m2s, unsigned s2m) {
#endif
progress();
- sim->ss = 1;
+ SET_SS(sim, 1);
sim->rdy = 1;
sim->activate = 1;
progress();
@@ -43,7 +49,7 @@ static void test_cross_transfer(unsigned m2s, unsigned s2m) {
progress_n(5);
sim->activate = 0;
- sim->ss = 0;
+ SET_SS(sim, 0);
sim->rdy = 0;
progress_n(5);
@@ -73,11 +79,14 @@ int main(int argc, char **argv) {
Verilated::traceEverOn(true);
sim = new Vsimtop;
- sim->ss = 0;
+ SET_SS(sim, 0);
sim->clk = 0;
sim->activate = 0;
sim->rdy = 0;
+ test_cross_transfer(0b101010101010101010101010, 0b010101010101010101010101);
+ test_cross_transfer(0b110011001100110011001100, 0b001100110011001100110011);
+
for (int i = 0; i < 10000; i++) {
unsigned m2s = rand() & ((1 << WID) - 1);
unsigned s2m = rand() & ((1 << WID) - 1);