rewrite entire test harness

1 files changed, 57 insertions, 30 deletions

diff --git a/tests/write_read.cpp b/tests/write_read.cpp
index 45bdc5a..2394b63 100644
--- a/tests/write_read.cpp
+++ b/tests/write_read.cpp
@@ -1,12 +1,21 @@
 #include <stdio.h>
 #include <verilated.h>
+#include "Vsimtop.h"
 
-VerilatedContext *ctx;
-TopModule *sim;
+Vsimtop *sim;
+
+uint32_t main_time = 0;
+
+double sc_time_stamp() {
+	return main_time;
+}
 
 static void progress() {
 	sim->eval();
-	ctx->timeInc(1);
+	main_time++;
+	sim->clk = !sim->clk;
+	sim->eval();
+	main_time++;
 	sim->clk = !sim->clk;
 }
 
@@ -15,49 +24,67 @@ static void progress_n(int f) {
 		progress();
 }
 
-int main(int argc, char **argv) {
-	ctx = new VerilatedContext;
-	ctx->traceEverOn(true);
-	ctx->commandArgs(argc, argv);
-	sim = new TopModule(ctx);
-	sim->ss = 0;
-	sim->clk = 0;
-	sim->activate = 0;
-	sim->rdy = 0;
+static void test_cross_transfer(unsigned m2s, unsigned s2m) {
+#ifndef SPI_MASTER_NO_WRITE
+	sim->master_to_slave = m2s;
+#endif
+#ifndef SPI_MASTER_NO_READ
+	sim->slave_to_master = s2m;
+#endif
 
-	progress_n(8);
+	progress();
 	sim->ss = 1;
 	sim->rdy = 1;
-	progress();
-
-#ifndef READ_ONLY
-	sim->data_ctrl = 0b110011011111001100011111;
-#endif
 	sim->activate = 1;
+	progress();
 
 	while (!sim->master_finished)
 		progress();
+
 	progress_n(5);
 	sim->activate = 0;
 	sim->ss = 0;
 	sim->rdy = 0;
 	progress_n(5);
 
-#ifndef READ_ONLY
-	sim->data_ctrl = 0xFE3456;
-	sim->activate = 1;
-	sim->ss = 1;
-	sim->rdy = 1;
-	while (!sim->master_finished)
-		progress();
-	progress_n(5);
-	sim->activate = 0;
+	if (sim->err) {
+		printf("slave error\n");
+	}
+
+#ifndef SPI_MASTER_NO_WRITE
+	if (sim->master_to_slave != sim->from_master) {
+		printf("(m2s) %lx != %lx\n", sim->master_to_slave, sim->from_master);
+	}
+#endif
+
+#ifndef SPI_MASTER_NO_READ
+	if (sim->slave_to_master != sim->from_slave) {
+		printf("(m2s) %lx != %lx\n", sim->slave_to_master, sim->from_slave);
+	}
+#endif
+
+}
+
+int main(int argc, char **argv) {
+	int r = 0;
+	(void)r;
+
+	Verilated::commandArgs(argc, argv);
+	Verilated::traceEverOn(true);
+
+	sim = new Vsimtop;
 	sim->ss = 0;
+	sim->clk = 0;
+	sim->activate = 0;
 	sim->rdy = 0;
-	progress_n(5);
-#endif
+
+	for (int i = 0; i < 10000; i++) {
+		unsigned m2s = rand() & ((1 << WID) - 1);
+		unsigned s2m = rand() & ((1 << WID) - 1);
+		test_cross_transfer(m2s, s2m);
+	}
 
 	sim->final();
 	delete sim;
-	return 0;
+	return r;
 }