diff options
| author |  Peter McGoron
| 2022-10-23 04:56:56 -0400 |
|---|---|---|
| committer | Peter McGoron
| 2022-10-23 04:56:56 -0400 |
| commit | 31fd1ded97e89e047dc7f032d8bab22fe56a92d2 (patch) | |
| tree | f4cbde753b92cb4f6c24639dda219159aae46ded /tests | |
| parent | add clean.sh (diff) | |
factor out code
Diffstat (limited to 'tests')
| -rwxr-xr-x | tests/mk.sh | 31 | ||||
| -rw-r--r-- | tests/simtop.v | 3 |
2 files changed, 18 insertions, 16 deletions
diff --git a/tests/mk.sh b/tests/mk.sh index f907668..51a9775 100755 --- a/tests/mk.sh +++ b/tests/mk.sh @@ -16,6 +16,7 @@ run_test() { -GPOLARITY=$POL -GPHASE=$PHASE -GWID=$WID -CFLAGS -DWID=$WID \ -GWID_LEN=$WIDLEN \ -DSPI_MASTER_TYPE=$MASTER_TYPE -DSPI_SLAVE_TYPE=$SLAVE_TYPE \ + -DVCDFILE="\"$DIR.vcd\"" \ --Mdir $DIR \ $EXTARG \ simtop.v write_read.cpp $MODS @@ -34,21 +35,21 @@ for POL in 0 1; do "../spi_master.v ../spi_slave.v" ) - ( \ - run_test $POL $PHASE \ - spi_master_no_write spi_slave_no_read \ - simtop_no_write_$POL$PHASE 24 \ - "../spi_master_no_write.v ../spi_slave_no_read.v" \ - "-DSPI_MASTER_NO_WRITE -CFLAGS -DSPI_MASTER_NO_WRITE" - ) - - ( \ - run_test $POL $PHASE \ - spi_master_no_read spi_slave_no_write \ - simtop_no_read_$POL$PHASE 24 \ - "../spi_master_no_read.v ../spi_slave_no_write.v" \ - "-DSPI_MASTER_NO_READ -CFLAGS -DSPI_MASTER_NO_READ" - ) +# ( \ +# run_test $POL $PHASE \ +# spi_master_no_write spi_slave_no_read \ +# simtop_no_write_$POL$PHASE 24 \ +# "../spi_master_no_write.v ../spi_slave_no_read.v" \ +# "-DSPI_MASTER_NO_WRITE -CFLAGS -DSPI_MASTER_NO_WRITE" +# ) +# +# ( \ +# run_test $POL $PHASE \ +# spi_master_no_read spi_slave_no_write \ +# simtop_no_read_$POL$PHASE 24 \ +# "../spi_master_no_read.v ../spi_slave_no_write.v" \ +# "-DSPI_MASTER_NO_READ -CFLAGS -DSPI_MASTER_NO_READ" +# ) done done diff --git a/tests/simtop.v b/tests/simtop.v index 91533fd..d47a802 100644 --- a/tests/simtop.v +++ b/tests/simtop.v @@ -46,7 +46,8 @@ reg slave_error; .POLARITY(POLARITY), .PHASE(PHASE), .WID(WID), - .WID_LEN(WID_LEN) + .WID_LEN(WID_LEN), + .CYCLE_HALF_WAIT(5) ) master ( .clk(clk), `ifndef SPI_MASTER_NO_WRITE |