rewrite entire test harness

10 files changed, 198 insertions, 232 deletions

diff --git a/tests/Makefile b/tests/Makefile
deleted file mode 100644
index 085cd92..0000000
--- a/tests/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-MODES=00 01 10 11
-
-all:
-	for i in ${MODES}; do \
-		make -f run_mode.makefile MODE="$$i"; \
-		make -f run_mode.makefile MODE="$$i" PREFIX="read_only_" MASTER_TYPE="_no_write" SLAVE_TYPE="_no_read"; \
-	done
-
-clean:
-	rm -rf obj_dir mode[01][01]* read_only_mode[01][01]*
diff --git a/tests/mk.sh b/tests/mk.sh
new file mode 100755
index 0000000..f907668
--- /dev/null
+++ b/tests/mk.sh
@@ -0,0 +1,54 @@
+#!/bin/sh
+
+run_test() {
+	POL=$1
+	PHASE=$2
+	MASTER_TYPE=$3
+	SLAVE_TYPE=$4
+	DIR=$5
+	WID=$6
+	MODS=$7
+	EXTARG=$8
+	WIDLEN=$(printf "import math\nprint(math.floor(math.log2($WID) + 1))" | python3 -)
+
+	verilator --cc --exe -I.. -Wall -Wno-unused --trace \
+		--top-module simtop \
+		-GPOLARITY=$POL -GPHASE=$PHASE -GWID=$WID -CFLAGS -DWID=$WID \
+		-GWID_LEN=$WIDLEN \
+		-DSPI_MASTER_TYPE=$MASTER_TYPE -DSPI_SLAVE_TYPE=$SLAVE_TYPE \
+		--Mdir $DIR \
+		$EXTARG \
+		simtop.v write_read.cpp $MODS
+
+	cd "$DIR"
+	make -f Vsimtop.mk
+	./Vsimtop
+}
+
+for POL in 0 1; do
+	for PHASE in 0 1; do
+		( \
+			run_test $POL $PHASE \
+			spi_master spi_slave \
+			simtop_$POL$PHASE 24 \
+			"../spi_master.v ../spi_slave.v"
+		)
+
+		( \
+			run_test $POL $PHASE \
+			spi_master_no_write spi_slave_no_read \
+			simtop_no_write_$POL$PHASE 24 \
+			"../spi_master_no_write.v ../spi_slave_no_read.v" \
+			"-DSPI_MASTER_NO_WRITE -CFLAGS -DSPI_MASTER_NO_WRITE"
+		)
+
+		( \
+			run_test $POL $PHASE \
+			spi_master_no_read spi_slave_no_write \
+			simtop_no_read_$POL$PHASE 24 \
+			"../spi_master_no_read.v ../spi_slave_no_write.v" \
+			"-DSPI_MASTER_NO_READ -CFLAGS -DSPI_MASTER_NO_READ"
+		)
+
+	done
+done
diff --git a/tests/mode_template.cpp b/tests/mode_template.cpp
deleted file mode 100644
index 4b46fb4..0000000
--- a/tests/mode_template.cpp
+++ /dev/null
@@ -1,3 +0,0 @@
-#include "Vmode@MODE@.h"
-using TopModule = Vmode@MODE@;
-#include "write_read.cpp"
diff --git a/tests/mode_template.v b/tests/mode_template.v
deleted file mode 100644
index 1df59b8..0000000
--- a/tests/mode_template.v
+++ /dev/null
@@ -1,34 +0,0 @@
-/* (c) Peter McGoron 2022
- * This Source Code Form is subject to the terms of the Mozilla Public
- * License, v.2.0. If a copy of the MPL was not distributed with this
- * file, You can obtain one at https://mozilla.org/MPL/2.0/.
- */
-
-module mode@MODE@ (
-	input clk,
-	input [23:0] data_ctrl,
-	input activate,
-	input ss,
-	input rdy,
-	output master_finished
-);
-
-spi_write_read
-#(
-	.POLARITY(@POLARITY@),
-	.PHASE(@PHASE@)
-) base (
-	.clk(clk),
-	.data_ctrl(data_ctrl),
-	.activate(activate),
-	.master_finished(master_finished),
-	.ss(ss),
-	.rdy(rdy)
-);
-
-initial begin
-	$dumpfile("mode@MODE@.vcd");
-	$dumpvars();
-end
-
-endmodule
diff --git a/tests/read_only_mode_template.cpp b/tests/read_only_mode_template.cpp
deleted file mode 100644
index d09a0be..0000000
--- a/tests/read_only_mode_template.cpp
+++ /dev/null
@@ -1,4 +0,0 @@
-#include "Vread_only_mode@MODE@.h"
-using TopModule = Vread_only_mode@MODE@;
-#define READ_ONLY
-#include "write_read.cpp"
diff --git a/tests/read_only_mode_template.v b/tests/read_only_mode_template.v
deleted file mode 100644
index cd10c7d..0000000
--- a/tests/read_only_mode_template.v
+++ /dev/null
@@ -1,57 +0,0 @@
-/* (c) Peter McGoron 2022
- * This Source Code Form is subject to the terms of the Mozilla Public
- * License, v.2.0. If a copy of the MPL was not distributed with this
- * file, You can obtain one at https://mozilla.org/MPL/2.0/.
- */
-
-module read_only_mode@MODE@ (
-	input clk,
-	input activate,
-	input ss,
-	input rdy,
-	output master_finished
-);
-
-wire miso;
-wire sck;
-wire ss_L = !ss;
-reg [23:0] from_slave_data;
-reg finished;
-reg err;
-
-spi_master_no_write
-#(
-	.POLARITY(@POLARITY@),
-	.PHASE(@PHASE@)
-) master (
-	.clk(clk),
-	.from_slave(from_slave_data),
-	.miso(miso),
-	.sck_wire(sck),
-	.finished(master_finished),
-	.arm(activate)
-);
-
-reg [23:0] to_master = 24'hF4325F;
-
-spi_slave_no_read
-#(
-	.POLARITY(@POLARITY@),
-	.PHASE(@PHASE@)
-) slave (
-	.clk(clk),
-	.sck(sck),
-	.ss_L(ss_L),
-	.to_master(to_master),
-	.miso(miso),
-	.finished(finished),
-	.rdy(rdy),
-	.err(finished)
-);
-
-initial begin
-	$dumpfile("read_only_mode@MODE@.vcd");
-	$dumpvars();
-end
-
-endmodule
diff --git a/tests/run_mode.makefile b/tests/run_mode.makefile
deleted file mode 100644
index 2b48053..0000000
--- a/tests/run_mode.makefile
+++ /dev/null
@@ -1,24 +0,0 @@
-# (c) Peter McGoron 2022
-# This Source Code Form is subject to the terms of the Mozilla Public
-# License, v.2.0. If a copy of the MPL was not distributed with this
-# file, You can obtain one at https://mozilla.org/MPL/2.0/.
-
-TESTBENCH_BASE=${PREFIX}mode${MODE}
-AUXFILES=../spi_master${MASTER_TYPE}.v ../spi_slave${SLAVE_TYPE}.v
-
-CPP_TESTBENCH=${TESTBENCH_BASE}.cpp
-WAVEFILE=${TESTBENCH_BASE}.vcd
-
-FILES=${TESTBENCH_BASE}.v ${AUXFILES} ${CPP_TESTBENCH}
-
-${WAVEFILE}: obj_dir/V${TESTBENCH_BASE}
-	./obj_dir/V${TESTBENCH_BASE}
-
-obj_dir/V${TESTBENCH_BASE}.mk: ${FILES}
-	verilator -I.. -Wall -Wno-unused -Wpedantic --trace --cc --exe ${FILES} --top ${TESTBENCH_BASE}
-obj_dir/V${TESTBENCH_BASE}: obj_dir/V${TESTBENCH_BASE}.mk
-	make -C obj_dir -f V${TESTBENCH_BASE}.mk
-${TESTBENCH_BASE}.v: mode_template.v
-	sed "s/@PHASE@/`echo ${MODE} | cut -c 2`/g; s/@POLARITY@/`echo ${MODE} | cut -c 1`/g; s/@MODE@/${MODE}/g" ${PREFIX}mode_template.v > ${TESTBENCH_BASE}.v
-${TESTBENCH_BASE}.cpp: mode_template.cpp
-	sed "s/@PHASE@/`echo ${MODE} | cut -c 2`/g; s/@POLARITY@/`echo ${MODE} | cut -c 1`/g; s/@MODE@/${MODE}/g" ${PREFIX}mode_template.cpp > ${TESTBENCH_BASE}.cpp
diff --git a/tests/simtop.v b/tests/simtop.v
new file mode 100644
index 0000000..91533fd
--- /dev/null
+++ b/tests/simtop.v
@@ -0,0 +1,87 @@
+/* (c) Peter McGoron 2022
+ * This Source Code Form is subject to the terms of the Mozilla Public
+ * License, v.2.0. If a copy of the MPL was not distributed with this
+ * file, You can obtain one at https://mozilla.org/MPL/2.0/.
+ */
+
+module simtop
+#(
+	parameter POLARITY = 0,
+	parameter PHASE = 0,
+	parameter WID = 24,
+	parameter WID_LEN = 5
+) (
+	input clk,
+`ifndef SPI_MASTER_NO_WRITE
+	input [WID-1:0] master_to_slave,
+	output [WID-1:0] from_master,
+`endif
+`ifndef SPI_MASTER_NO_READ
+	input [WID-1:0] slave_to_master,
+	output [WID-1:0] from_slave,
+`endif
+	input activate,
+	input ss,
+	input rdy,
+	output master_finished,
+	output err
+);
+
+`ifndef SPI_MASTER_NO_READ
+wire miso;
+`endif
+
+`ifndef SPI_MASTER_NO_WRITE
+wire mosi;
+`endif
+
+wire sck;
+wire ss_L = !ss;
+
+reg slave_finished;
+reg slave_error;
+
+`SPI_MASTER_TYPE
+#(
+	.POLARITY(POLARITY),
+	.PHASE(PHASE),
+	.WID(WID),
+	.WID_LEN(WID_LEN)
+) master (
+	.clk(clk),
+`ifndef SPI_MASTER_NO_WRITE
+	.to_slave(master_to_slave),
+	.mosi(mosi),
+`endif
+`ifndef SPI_MASTER_NO_READ
+	.from_slave(from_slave),
+	.miso(miso),
+`endif
+	.sck_wire(sck),
+	.finished(master_finished),
+	.arm(activate)
+);
+
+`SPI_SLAVE_TYPE #(
+	.POLARITY(POLARITY),
+	.PHASE(PHASE),
+	.WID(WID),
+	.WID_LEN(WID_LEN)
+) slave (
+	.clk(clk),
+	.sck(sck),
+	.ss_L(ss_L),
+`ifndef SPI_MASTER_NO_WRITE
+	.from_master(from_master),
+	.mosi(mosi),
+`endif
+`ifndef SPI_MASTER_NO_READ
+	.to_master(slave_to_master),
+	.miso(miso),
+`endif
+	.finished(slave_finished),
+	.rdy(rdy),
+	.err(err)
+);
+
+endmodule
diff --git a/tests/spi_write_read.v b/tests/spi_write_read.v
deleted file mode 100644
index efd9e88..0000000
--- a/tests/spi_write_read.v
+++ /dev/null
@@ -1,70 +0,0 @@
-/* (c) Peter McGoron 2022
- * This Source Code Form is subject to the terms of the Mozilla Public
- * License, v.2.0. If a copy of the MPL was not distributed with this
- * file, You can obtain one at https://mozilla.org/MPL/2.0/.
- */
-
-module spi_write_read
-#(
-	parameter POLARITY = 0,
-	parameter PHASE = 0
-)
-(
-	input clk,
-	input [23:0] data_ctrl,
-	input activate,
-	input ss,
-	input rdy,
-	output master_finished
-);
-
-wire miso;
-wire mosi;
-wire sck;
-wire ss_L = !ss;
-
-reg [23:0] from_slave_data;
-reg slave_finished;
-reg slave_error;
-
-spi_master
-#(
-	.POLARITY(POLARITY),
-	.PHASE(PHASE)
-) master (
-	.clk(clk),
-	.to_slave(data_ctrl),
-	.from_slave(from_slave_data),
-	.miso(miso),
-	.mosi(mosi),
-	.sck_wire(sck),
-	.finished(master_finished),
-	.arm(activate)
-);
-
-reg [23:0] data_from_master;
-reg [23:0] data_to_master = 24'b111011011100010101010101;
-
-spi_slave #(
-	.POLARITY(POLARITY),
-	.PHASE(PHASE)
-) slave (
-	.clk(clk),
-	.sck(sck),
-	.ss_L(ss_L),
-	.from_master(data_from_master),
-	.to_master(data_to_master),
-	.mosi(mosi),
-	.miso(miso),
-	.finished(slave_finished),
-	.rdy(rdy),
-	.err(slave_error)
-);
-
-always @ (posedge clk) begin
-	if (slave_finished) begin
-		data_to_master <= data_from_master;
-	end
-end
-
-endmodule
diff --git a/tests/write_read.cpp b/tests/write_read.cpp
index 45bdc5a..2394b63 100644
--- a/tests/write_read.cpp
+++ b/tests/write_read.cpp
@@ -1,12 +1,21 @@
 #include <stdio.h>
 #include <verilated.h>
+#include "Vsimtop.h"
 
-VerilatedContext *ctx;
-TopModule *sim;
+Vsimtop *sim;
+
+uint32_t main_time = 0;
+
+double sc_time_stamp() {
+	return main_time;
+}
 
 static void progress() {
 	sim->eval();
-	ctx->timeInc(1);
+	main_time++;
+	sim->clk = !sim->clk;
+	sim->eval();
+	main_time++;
 	sim->clk = !sim->clk;
 }
 
@@ -15,49 +24,67 @@ static void progress_n(int f) {
 		progress();
 }
 
-int main(int argc, char **argv) {
-	ctx = new VerilatedContext;
-	ctx->traceEverOn(true);
-	ctx->commandArgs(argc, argv);
-	sim = new TopModule(ctx);
-	sim->ss = 0;
-	sim->clk = 0;
-	sim->activate = 0;
-	sim->rdy = 0;
+static void test_cross_transfer(unsigned m2s, unsigned s2m) {
+#ifndef SPI_MASTER_NO_WRITE
+	sim->master_to_slave = m2s;
+#endif
+#ifndef SPI_MASTER_NO_READ
+	sim->slave_to_master = s2m;
+#endif
 
-	progress_n(8);
+	progress();
 	sim->ss = 1;
 	sim->rdy = 1;
-	progress();
-
-#ifndef READ_ONLY
-	sim->data_ctrl = 0b110011011111001100011111;
-#endif
 	sim->activate = 1;
+	progress();
 
 	while (!sim->master_finished)
 		progress();
+
 	progress_n(5);
 	sim->activate = 0;
 	sim->ss = 0;
 	sim->rdy = 0;
 	progress_n(5);
 
-#ifndef READ_ONLY
-	sim->data_ctrl = 0xFE3456;
-	sim->activate = 1;
-	sim->ss = 1;
-	sim->rdy = 1;
-	while (!sim->master_finished)
-		progress();
-	progress_n(5);
-	sim->activate = 0;
+	if (sim->err) {
+		printf("slave error\n");
+	}
+
+#ifndef SPI_MASTER_NO_WRITE
+	if (sim->master_to_slave != sim->from_master) {
+		printf("(m2s) %lx != %lx\n", sim->master_to_slave, sim->from_master);
+	}
+#endif
+
+#ifndef SPI_MASTER_NO_READ
+	if (sim->slave_to_master != sim->from_slave) {
+		printf("(m2s) %lx != %lx\n", sim->slave_to_master, sim->from_slave);
+	}
+#endif
+
+}
+
+int main(int argc, char **argv) {
+	int r = 0;
+	(void)r;
+
+	Verilated::commandArgs(argc, argv);
+	Verilated::traceEverOn(true);
+
+	sim = new Vsimtop;
 	sim->ss = 0;
+	sim->clk = 0;
+	sim->activate = 0;
 	sim->rdy = 0;
-	progress_n(5);
-#endif
+
+	for (int i = 0; i < 10000; i++) {
+		unsigned m2s = rand() & ((1 << WID) - 1);
+		unsigned s2m = rand() & ((1 << WID) - 1);
+		test_cross_transfer(m2s, s2m);
+	}
 
 	sim->final();
 	delete sim;
-	return 0;
+	return r;
 }