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# Verilog SPI
Verilog SPI master and slave that supports all modes and variable width
via parameters.
## License
All code in this project is licensed to the terms of the Mozilla Public
License, v.2.0. A copy of this license may be found in the file `COPYING`. You
can obtain one at https://mozilla.org/MPL/2.0/.
All Verilog source in this project is dual-licensed under the MPL v2.0
and the CERN-OHL-W v2.0 (or any later version).
## Tests
Run `./mk.sh` in `tests/` to generate and run tests.
## Modules
"master_no_read" and "slave_no_write" have no Master In, Slave Out ("miso")
wires (and no corresponding shift registers), while "master_no_write"
and "slave_no_read" have no Master Out, Slave In ("mosi") wires. This
is for compatability for "SPI compatible" devices that are read only.
"master_ss" and others include a timer that will assert the Slave Select
pin and wait a set number of clock cycles before starting the SPI transfer.
## SPI Modes
Modes are denoted by `modePH`, where `P` is the polarity (0 for normal,
1 for inverted) and `H` for phase:
* `H = 0` means the device reads on a rising edge and writes on a falling
edge.
* `H = 1` means the device reads on a falling edge and writes on a rising
edge.
Although these modules support all SPI modes, they are labeled slightly
differently from other SPI modes. The phase factor is denoted in terms
of falling and rising edges, not in terms of leading and trailing edges.
This means that polarity also flips the phase term, so a mode 3 device
is a mode 10 device. Devices with regular clock polarity are unaffected,
so a mode 0 device is a mode 00 device, and a mode 1 device is a mode
01 device.
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