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/* (c) Peter McGoron 2022
* This Source Code Form is subject to the terms of the Mozilla Public
* License, v.2.0. If a copy of the MPL was not distributed with this
* file, You can obtain one at https://mozilla.org/MPL/2.0/.
*/
module mode00 (
input clk,
input [23:0] data_ctrl,
input activate,
input ss,
input rdy,
output master_finished
);
spi_write_read
#(
.POLARITY(0),
.PHASE(0)
) base (
.clk(clk),
.data_ctrl(data_ctrl),
.activate(activate),
.master_finished(master_finished),
.ss(ss),
.rdy(rdy)
);
initial begin
$dumpfile("mode00.vcd");
$dumpvars();
end
endmodule
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