Hardware

VexRiscv

Assembly 0 0

A FPGA friendly 32 bit RISC-V CPU implementation

fpga verilog soc softcore spinalhdl cpu vhdl riscv

Updated 2024-10-21 11:25:33 -04:00

liteeth

Python 0 0

Small footprint and configurable Ethernet core

Updated 2024-10-18 12:27:54 -04:00

litex

C 0 0

Build your hardware, easily!

fpga hardware system-on-chip

Updated 2024-10-17 13:45:44 -04:00

f4pga

Python 0 0

FOSS Flow For FPGA

documentation sphinx symbiflow

Updated 2024-10-15 12:15:18 -04:00

litex-boards

Python 0 0

LiteX boards files

Updated 2024-10-10 02:57:56 -04:00

litedram

Python 0 0

Small footprint and configurable DRAM core

Updated 2024-09-27 03:34:36 -04:00

litescope

Python 0 0

Small footprint and configurable embedded FPGA logic analyzer

Updated 2024-09-20 06:35:27 -04:00

picorv32

Verilog 0 0

PicoRV32 - A Size-Optimized RISC-V CPU

Updated 2024-06-17 02:20:13 -04:00

f4pga-examples

Verilog 0 0

Example designs showing different ways to use F4PGA toolchains.

fpga f4pga fpga-designs litex symbiflow-toolchains verilog conda-packages vexriscv

Updated 2024-03-27 07:22:52 -04:00