VexRiscv/scripts/Murax/arty_a7/vivado_params.tcl

mirror of https://github.com/SpinalHDL/VexRiscv.git synced 2025-01-03 03:43:39 -05:00
set outputdir ./vivado_project
set part "xc7a35ticsg324-1L"
set base ".."
set projectName "fpga"
set topv "$base/../../../Murax.v"
Revert "Revert "Merge branch 'master' into dev"" This reverts commit c01c2567578b18e4fec4466d6db3ce644b8eeede. Fix dBusCachedPlugin relaxedMemoryTranslationRegister when mmu translation is done in the execute stage 2020-01-29 16:37:09 -05:00			`set outputdir ./vivado_project`
			`set part "xc7a35ticsg324-1L"`
			`set base ".."`
			`set projectName "fpga"`
			`set topv "$base/../../../Murax.v"`