54 lines
1.6 KiB
Plaintext
54 lines
1.6 KiB
Plaintext
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class PcManagerSimple(resetVector : BigInt,pcWidth : Int,fastFetchCmdPcCalculation : Boolean) extends Plugin[SpinalRiscv] with PcManagerService{
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import StandardStageables._
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//FetchService interface
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case class JumpInfo(pc: UInt, cond: Bool, stage: Stage)
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val jumpInfos = ArrayBuffer[JumpInfo]()
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override def jumpTo(pc: UInt, cond: Bool, stage: Stage): Unit = jumpInfos += JumpInfo(pc,cond,stage)
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override def build(pipeline: SpinalRiscv): Unit = {
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import pipeline.prefetch
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prefetch.plug(new Area {
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import prefetch._
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//PC calculation without Jump
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val pcReg = Reg(UInt(pcWidth bit)) init(resetVector)
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val inc = RegInit(False)
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val pc = if(fastFetchCmdPcCalculation){
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val pcPlus4 = pcReg + 4
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pcPlus4.addAttribute("keep")
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Mux(inc,pcPlus4,pcReg)
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}else{
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pcReg + (inc ? U(4) | U(0))
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}
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//Stage always valid
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arbitration.isValid := True
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//FetchService hardware implementation
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val jumpInfoSorted = jumpInfos.sortWith((a,b) => pipeline.indexOf(a.stage) > pipeline.indexOf(b.stage))
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val jumpRequestValids = jumpInfoSorted.map(_.cond)
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val jumpRequestPcs = jumpInfoSorted.map(_.pc)
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val pcLoad = Flow(pcReg)
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pcLoad.valid := jumpInfos.foldLeft(False)(_ || _.cond)
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pcLoad.payload := MuxOH(jumpRequestValids,jumpRequestPcs)
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//Register managments
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when(pcLoad.valid){
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pc := pcLoad.payload
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inc := False
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pcReg := pc
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}
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when(arbitration.isFiring){
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inc := True
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pcReg := pc
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}
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//Pipeline insertions
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insert(PC) := pc
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})
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}
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}
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