Changing the above lines, removes the Murax SoC’s JTAG ports as pins of the FPGA and inserts the BSCANE2 Xilinx
Debug IP to which the JTAG signals are now connected.
* Add the following import statement at the beginning of `Murax.scala`:
```
import spinal.lib.com.jtag.JtagTapInstructionCtrl
```
With these changes in place, you generate the SoC with a demo program already in ram by use of:
```
sbt "runMain vexriscv.demo.MuraxWithRamInit"
```
A Verilog file is generated with the name `Murax.v` next to four `.bin` files inside the `VexRiscv` folder. These
files are the input to the Xilinx FPGA synthesis. Inside the `Murax.v` file, we can see that the BSCANE2 ports are
instantiated, confirming that the BSCANE2 has successfully been instantiated within the Murax SoC as a debug brige
to JTAG.
## 3. Xilinx Vivado - Programming Arty A7 FPGA
There are many applications to program a FPGA. In our work we referred to the freely available Xilinx Vivado 2020
application to synthesize and program the FPGA. Vivado is readily available at Xilinx website and free of cost to
download. This document assumes that the reader is able to setup and execute FPGA synthesis projects. The
following is not a step by step tutorial, but gives general guiding information.
### Programming the FPGA
* Create a new project and choose the board. In our case it is the Arty A7-35 (`xc7a35ticsg324-1L`).
* Copy the mentioned files (.v and .bin) of the previous section from the Vexriscv folder into the Vivado project
in e.g. the path: `project_name.srcs\sources_1\imports\Downloads`
* Create a toplevel file by instantiating Murax I/O ports in it to blink the LED’s on the Digilent board. (Note: The program to blink the LED’s is already present in the four `.bin` files with the `Murax.v` file). The toplevel file and constraint `arty_a7.xdc` file, if required, can be found and reused from the path: `VexRiscv/scripts/Murax/arty_a7`, but you need to make sure that all the JTAG ports of Murax are commented or deleted in the toplevel file. Remember: we removed them in Section 2 and connected them internally to the BSCANE2 debug bridge.
* Be aware that line numbers as given could move with future changes to the file. The lines to remove from toplevel file are:
You can take it from ... https://github.com/SpinalHDL/SaxonSoc/blob/dev-0.3/bsp/digilent/ArtyA7SmpLinux/openocd/usb_connect.cfg ... without modifications as we would say. Be aware that it includes the two files `xilinx-xc7.cfg` and `jtagspi.cfg` which are part of the OpenOCD project ... https://github.com/riscv/riscv-openocd/tree/riscv/tcl/cpld , but make sure to check the path for the files. If required, adapt the find and path for the lines:
Info : Listening on port 4444 for telnet connections
```
* Information on setting up a riscv compiler and debugger toolchain are to be found at:
https://github.com/riscv/riscv-gnu-toolchain
* With openocd running you can now connect a debugger to `port 3333`.
* A demonstration software to compile and debug with the Murax SoC can be found at https://github.com/SpinalHDL/VexRiscvSocSoftware in the path `VexRiscvSocSoftware/projects/murax/demo`. With a `make` you create the `.elf` in the `build` directory from which you then give the command:
```
riscv64-unknown-elf-gdb demo.elf
```
* The riscv debugger is started with the `demo.elf` program and is ready to be connected to the CPU. Do so by issuing the following command in its window:
*`target remote localhost:3333` This command will connect the GDB server to OpenOCD
*`load` This command will load the program into the FPGA. Whenever you decide to make changes to the demo software and recompiled it, you need to upload the resulting new executable to the CPU in this way.
*`monitor reset halt` This command resets the Murax CPU and halts it to receive further commands.
*`continue` From here on you should be able to execute a regular debug session with your VexRiscv based Murax SoC on the FPGA.
