106 lines
3.3 KiB
Markdown
106 lines
3.3 KiB
Markdown
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# Intel VJTAG
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*By Levi Walker (@LYWalker)*
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Intel VJTAG allows JTAG communication with the FPGA fabric of Altera devices through the standard USB cable using the onboard USB-Blaster. This avoids the needs to breakout the JTAG signals to the GPIO and use a dedicated external debugger.
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## How to use VJTAG with Briey
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In Briey.scala remove the following lines (note: line numbers may differ, depending on edits):
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```
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[185] val jtag = slave(Jtag())
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...
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[466] val tcpJtag = JtagTcp(
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[467] jtag = dut.io.jtag,
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[468] jtagClkPeriod = jtagClkPeriod
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[469] )
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```
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Then VJAG can be added in two ways.
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### Method 1
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Replace the following line in Briey.scala:
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```
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[311] io.jtag <> plugin.io.bus.fromJtag()
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```
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with
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```
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[311] plugin.io.bus.fromVJtag()
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```
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### Method 2
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Replace the following line in Briey.scala:
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```
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[311] io.jtag <> plugin.io.bus.fromJtag()
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```
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with
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```
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[311] val tap = new sld_virtual_jtag(2)
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[312] val jtagCtrl = tap.toJtagTapInstructionCtrl()
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[313] jtagCtrl <> plugin.io.bus.fromJtagInstructionCtrl(ClockDomain(tap.io.tck),0)
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```
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And add
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```
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import spinal.lib.blackbox.altera.sld_virtual_jtag
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```
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to the imports at the top of the file.
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This uses the existing JtagInstructionCtrl architecture and communicates using DR headers.
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## Using OpenOCD
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First, clone and setup openocd with the steps as provided by https://github.com/SpinalHDL/openocd_riscv
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Then in tcl/target/Briey.cfg set `_USE_VJTAG` to 1:
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```
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[3] set _USE_VJTAG 1
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```
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Then if you used Method 1 above uncomment line 25:
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```
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[25] vexriscv jtagMapping 0 1 0 0 0 0
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```
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If you used Method 2 uncomment line 27:
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```
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[27] vexriscv jtagMapping 0 0 0 1 2 2
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```
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If the board uses USB-Blaster2 then run OpenOCD in shell using:
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```
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openocd -c "set CPU0_YAML ../VexRiscv/cpu0.yaml" \
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-f tcl/interface/altera-usb-blaster2.cfg \
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-f tcl/interface/soc_init.cfg
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```
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Note: you may need to edit `tcl/interface/altera-usb-blaster2.cfg` with your quartus path.
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If using an older board using USB-Blaster run using:
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```
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openocd -c "set CPU0_YAML ../VexRiscv/cpu0.yaml" -f tcl/interface/altera-usb-blaster.cfg -f tcl/interface/Briey.cfg
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```
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On success it should look something like:
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```
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Open On-Chip Debugger 0.11.0+dev-02588-gb10abb4b1 (2022-11-07-13:38)
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Licensed under GNU GPL v2
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For bug reports, read
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http://openocd.org/doc/doxygen/bugs.html
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../../Verilog/cpu0.yaml
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Info : only one transport option; autoselect 'jtag'
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DEPRECATED! use 'adapter speed' not 'adapter_khz'
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DEPRECATED! use 'adapter srst delay' not 'adapter_nsrst_delay'
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Info : set servers polling period to 50ms
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Info : usb blaster interface using libftdi
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Info : This adapter doesn't support configurable speed
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Info : JTAG tap: fpgasoc.fpga.tap tap/device found: 0x020f20dd (mfg: 0x06e (Altera), part: 0x20f2, ver: 0x0)
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[fpga_spinal.cpu0] Target successfully examined.
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Info : starting gdb server for fpga_spinal.cpu0 on 3333
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Info : Listening on port 3333 for gdb connections
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requesting target halt and executing a soft reset
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Info : Listening on port 6666 for tcl connections
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Info : Listening on port 4444 for telnet connections
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```
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From this point on attach a gdb connection and debug the board as usual.
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*NOTE: You may need to add your boards FPGA ID to line [21] of Briey.cfg, simply append it to the other expected ids using: `-expected-id <your id>`. The IDs for the DE1-SoC and DE0 have already been added.*
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