fpu eq lt le pass testfloat
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6170243283
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008fadeaa9
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@ -16,6 +16,8 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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val port = Vec(slave(FpuPort(p)), portCount)
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}
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// io.port(0).completion.flag.setAsDirectionLess.allowDirectionLessIo
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val portCountWidth = log2Up(portCount)
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val Source = HardType(UInt(portCountWidth bits))
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val exponentOne = (1 << p.internalExponentSize-1) - 1
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@ -622,6 +624,17 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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}
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}
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// val useRs1 = List(FpuOpcode.CMP).map(input.opcode === _).orR
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// val useRs2 = List(FpuOpcode.CMP).map(input.opcode === _).orR
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val onlySignalingNan = input.arg === 2
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val rs1Nan = input.rs1.isNan
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val rs2Nan = input.rs2.isNan
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val rs1NanNv = input.rs1.isNan && !(onlySignalingNan && input.rs1.isQuiet)
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val rs2NanNv = input.rs2.isNan && !(onlySignalingNan && input.rs2.isQuiet)
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val nv = input.opcode === FpuOpcode.CMP && (rs1NanNv || rs2NanNv)
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flag.NV setWhen(input.valid && nv)
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input.ready := !halt && (toFpuRf ? rfOutput.ready | io.port.map(_.rsp.ready).read(input.source))
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for(i <- 0 until portCount){
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def rsp = io.port(i).rsp
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@ -39,7 +39,7 @@ class FpuTest extends FunSuite{
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val config = SimConfig
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config.allOptimisation
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config.withFstWave
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// config.withFstWave
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config.compile(new FpuCore(portCount, p){
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for(i <- 0 until portCount) out(Bits(5 bits)).setName(s"flagAcc$i") := io.port(i).completion.flag.asBits
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setDefinitionName("FpuCore")
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@ -84,13 +84,21 @@ class FpuTest extends FunSuite{
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val s = new Scanner(next)
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(b2f(s.nextLong(16).toInt), s.nextLong(16).toInt, s.nextInt(16))
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}
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def f32_f32_i32 = {
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val s = new Scanner(next)
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val a,b,c = (s.nextLong(16).toInt)
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(b2f(a), b2f(b), c, s.nextInt(16))
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}
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val RNE = build("-rnear_even")
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val RTZ = build("-rminMag")
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val RDN = build("-rmin")
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val RUP = build("-rmax")
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val RMM = build("-rnear_maxMag")
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val all = List(RNE, RTZ, RDN, RUP, RMM)
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}
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lazy val RAW = build("")
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lazy val RNE = build("-rnear_even")
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lazy val RTZ = build("-rminMag")
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lazy val RDN = build("-rmin")
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lazy val RUP = build("-rmax")
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lazy val RMM = build("-rnear_maxMag")
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lazy val all = List(RNE, RTZ, RDN, RUP, RMM, RAW)
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def kill = all.foreach(_.kill)
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def apply(rounding : FpuRoundMode.E) = rounding match {
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case FpuRoundMode.RNE => RNE
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@ -109,6 +117,9 @@ class FpuTest extends FunSuite{
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val i2f = new TestCase("i32_to_f32")
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val f2ui = new TestCase("f32_to_ui32")
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val f2i = new TestCase("f32_to_i32")
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val eq = new TestCase("f32_eq")
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val lt = new TestCase("f32_lt")
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val le = new TestCase("f32_le")
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}
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val cpus = for(id <- 0 until portCount) yield new {
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@ -126,9 +137,12 @@ class FpuTest extends FunSuite{
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def softAssert(cond : Boolean, msg : String) = if(!cond)println(msg)
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def flagMatch(ref : Int, value : Float, report : String): Unit ={
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waitUntil(pendingMiaou == 0)
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val patch = if(value.abs == 1.17549435E-38f) ref & ~2 else ref
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assert(flagAccumulator == patch, s"Flag missmatch dut=$flagAccumulator ref=$patch $report")
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flagMatch(ref, patch, report)
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}
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def flagMatch(ref : Int, report : String): Unit ={
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waitUntil(pendingMiaou == 0)
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assert(flagAccumulator == ref, s"Flag missmatch dut=$flagAccumulator ref=$ref $report")
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flagAccumulator = 0
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}
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@ -257,8 +271,8 @@ class FpuTest extends FunSuite{
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}
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def cmp(rs1 : Int, rs2 : Int)(body : FpuRsp => Unit): Unit ={
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fpuF2i(rs1, rs2, FpuOpcode.CMP, 1, FpuRoundMode.elements.randomPick())(body)
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def cmp(rs1 : Int, rs2 : Int, arg : Int = 1)(body : FpuRsp => Unit): Unit ={
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fpuF2i(rs1, rs2, FpuOpcode.CMP, arg, FpuRoundMode.elements.randomPick())(body)
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}
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def f2i(rs1 : Int, signed : Boolean, rounding : FpuRoundMode.E = FpuRoundMode.RNE)(body : FpuRsp => Unit): Unit ={
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@ -620,6 +634,23 @@ class FpuTest extends FunSuite{
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}
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}
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def testCmpExact(a : Float, b : Float, ref : Int, flag : Int, arg : Int): Unit ={
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val rs = new RegAllocator()
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val rs1, rs2, rs3 = rs.allocate()
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val rd = Random.nextInt(32)
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load(rs1, a)
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load(rs2, b)
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cmp(rs1, rs2, arg){rsp =>
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val v = rsp.value.toLong
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assert(v === ref, f"cmp($a, $b, $arg) = $v, $ref")
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}
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flagMatch(flag,f"$a < $b $ref $flag ${f2b(a).toHexString} ${f2b(b).toHexString}")
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}
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def testLe(a : Float, b : Float, ref : Int, flag : Int) = testCmpExact(a,b,ref,flag, 0)
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def testEq(a : Float, b : Float, ref : Int, flag : Int) = testCmpExact(a,b,ref,flag, 2)
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def testLt(a : Float, b : Float, ref : Int, flag : Int) = testCmpExact(a,b,ref,flag, 1)
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def testFmv_x_w(a : Float): Unit ={
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val rs = new RegAllocator()
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val rs1, rs2, rs3 = rs.allocate()
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@ -719,6 +750,21 @@ class FpuTest extends FunSuite{
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val binaryOps = List[(Int,Int,Int,FpuRoundMode.E) => Unit](add, sub, mul)
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for(_ <- 0 until 100000){
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val (a,b,i,f) = f32.le.RAW.f32_f32_i32
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testLe(a,b,i, f)
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}
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for(_ <- 0 until 100000){
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val (a,b,i,f) = f32.lt.RAW.f32_f32_i32
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testLt(a,b,i, f)
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}
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for(_ <- 0 until 100000){
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val (a,b,i,f) = f32.eq.RAW.f32_f32_i32
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testEq(a,b,i, f)
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}
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println("Cmp done")
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testF2iExact(-2.14748365E9f, -2147483648, 0, true, FpuRoundMode.RDN)
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