Add SimpleBusInterconnect
This commit is contained in:
Dolu1990
parent
4ed4af6a3e
commit
00bf84b7f8
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@ -9,68 +9,6 @@ import spinal.lib.misc.{HexTools, InterruptCtrl, Prescaler, Timer}
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import spinal.lib._
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import spinal.lib._
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import vexriscv.plugin.{DBusSimpleBus, IBusSimpleBus}
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import vexriscv.plugin.{DBusSimpleBus, IBusSimpleBus}
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case class SimpleBusConfig(addressWidth : Int, dataWidth : Int)
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case class SimpleBusCmd(config : SimpleBusConfig) extends Bundle{
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val wr = Bool
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val address = UInt(config.addressWidth bits)
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val data = Bits(config.dataWidth bits)
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val mask = Bits(4 bit)
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}
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case class SimpleBusRsp(config : SimpleBusConfig) extends Bundle{
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val data = Bits(config.dataWidth bits)
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}
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object SimpleBus{
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def apply(addressWidth : Int, dataWidth : Int) = new SimpleBus(SimpleBusConfig(addressWidth, dataWidth))
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}
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case class SimpleBus(config : SimpleBusConfig) extends Bundle with IMasterSlave {
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val cmd = Stream(SimpleBusCmd(config))
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val rsp = Flow(SimpleBusRsp(config))
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override def asMaster(): Unit = {
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master(cmd)
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slave(rsp)
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}
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def <<(m : SimpleBus) : Unit = {
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val s = this
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assert(m.config.addressWidth >= s.config.addressWidth)
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assert(m.config.dataWidth == s.config.dataWidth)
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s.cmd.valid := m.cmd.valid
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s.cmd.wr := m.cmd.wr
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s.cmd.address := m.cmd.address.resized
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s.cmd.data := m.cmd.data
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s.cmd.mask := m.cmd.mask
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m.cmd.ready := s.cmd.ready
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m.rsp.valid := s.rsp.valid
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m.rsp.data := s.rsp.data
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}
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def >>(s : SimpleBus) : Unit = s << this
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def cmdM2sPipe(): SimpleBus = {
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val ret = cloneOf(this)
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this.cmd.m2sPipe() >> ret.cmd
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this.rsp << ret.rsp
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ret
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}
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def cmdS2mPipe(): SimpleBus = {
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val ret = cloneOf(this)
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this.cmd.s2mPipe() >> ret.cmd
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this.rsp << ret.rsp
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ret
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}
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def rspPipe(): SimpleBus = {
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val ret = cloneOf(this)
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this.cmd >> ret.cmd
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this.rsp << ret.rsp.stage()
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ret
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}
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}
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class MuraxMasterArbiter(simpleBusConfig : SimpleBusConfig) extends Component{
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class MuraxMasterArbiter(simpleBusConfig : SimpleBusConfig) extends Component{
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val io = new Bundle{
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val io = new Bundle{
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val iBus = slave(IBusSimpleBus(false))
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val iBus = slave(IBusSimpleBus(false))
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@ -0,0 +1,280 @@
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package vexriscv.demo
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import spinal.core._
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import spinal.lib.bus.misc._
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import spinal.lib._
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import scala.collection.mutable
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import scala.collection.mutable.ArrayBuffer
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case class SimpleBusConfig(addressWidth : Int, dataWidth : Int)
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case class SimpleBusCmd(config : SimpleBusConfig) extends Bundle{
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val wr = Bool
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val address = UInt(config.addressWidth bits)
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val data = Bits(config.dataWidth bits)
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val mask = Bits(4 bit)
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}
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case class SimpleBusRsp(config : SimpleBusConfig) extends Bundle{
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val data = Bits(config.dataWidth bits)
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}
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object SimpleBus{
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def apply(addressWidth : Int, dataWidth : Int) = new SimpleBus(SimpleBusConfig(addressWidth, dataWidth))
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}
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case class SimpleBus(config : SimpleBusConfig) extends Bundle with IMasterSlave {
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val cmd = Stream(SimpleBusCmd(config))
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val rsp = Flow(SimpleBusRsp(config))
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override def asMaster(): Unit = {
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master(cmd)
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slave(rsp)
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}
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def <<(m : SimpleBus) : Unit = {
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val s = this
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assert(m.config.addressWidth >= s.config.addressWidth)
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assert(m.config.dataWidth == s.config.dataWidth)
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s.cmd.valid := m.cmd.valid
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s.cmd.wr := m.cmd.wr
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s.cmd.address := m.cmd.address.resized
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s.cmd.data := m.cmd.data
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s.cmd.mask := m.cmd.mask
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m.cmd.ready := s.cmd.ready
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m.rsp.valid := s.rsp.valid
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m.rsp.data := s.rsp.data
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}
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def >>(s : SimpleBus) : Unit = s << this
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def cmdM2sPipe(): SimpleBus = {
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val ret = cloneOf(this)
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this.cmd.m2sPipe() >> ret.cmd
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this.rsp << ret.rsp
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ret
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}
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def cmdS2mPipe(): SimpleBus = {
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val ret = cloneOf(this)
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this.cmd.s2mPipe() >> ret.cmd
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this.rsp << ret.rsp
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ret
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}
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def rspPipe(): SimpleBus = {
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val ret = cloneOf(this)
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this.cmd >> ret.cmd
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this.rsp << ret.rsp.stage()
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ret
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}
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}
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object SimpleBusArbiter{
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def apply(inputs : Seq[SimpleBus], pendingRspMax : Int): SimpleBus = {
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val c = SimpleBusArbiter(inputs.head.config, inputs.size, pendingRspMax)
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(inputs, c.io.inputs).zipped.foreach(_ <> _)
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c.io.output
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}
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}
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case class SimpleBusArbiter(simpleBusConfig : SimpleBusConfig, portCount : Int, pendingRspMax : Int) extends Component{
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val io = new Bundle{
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val inputs = Vec(slave(SimpleBus(simpleBusConfig)), portCount)
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val output = master(SimpleBus(simpleBusConfig))
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}
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val logic = if(portCount == 1) new Area{
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io.output << io.inputs(0)
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} else new Area {
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val arbiter = StreamArbiterFactory.lowerFirst.transactionLock.build(SimpleBusCmd(simpleBusConfig), portCount)
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(arbiter.io.inputs, io.inputs).zipped.foreach(_ <> _.cmd)
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val (outputCmdFork, routeCmdFork) = StreamFork2(arbiter.io.output)
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io.output.cmd << outputCmdFork
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val rspRoute = routeCmdFork.translateWith(arbiter.io.chosen).throwWhen(routeCmdFork.wr).queueLowLatency(size = pendingRspMax, latency = 1)
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rspRoute.ready := io.output.rsp.valid
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for ((input, id) <- io.inputs.zipWithIndex) {
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input.rsp.valid := io.output.rsp.valid && rspRoute.payload === id
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input.rsp.payload := io.output.rsp.payload
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}
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}
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}
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class SimpleBusSlaveFactory(bus: SimpleBus) extends BusSlaveFactoryDelayed{
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bus.cmd.ready := True
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val readAtCmd = Flow(Bits(bus.config.dataWidth bits))
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val readAtRsp = readAtCmd.stage()
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val askWrite = (bus.cmd.valid && bus.cmd.wr).allowPruning()
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val askRead = (bus.cmd.valid && !bus.cmd.wr).allowPruning()
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val doWrite = (askWrite && bus.cmd.ready).allowPruning()
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val doRead = (askRead && bus.cmd.ready).allowPruning()
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bus.rsp.valid := readAtRsp.valid
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bus.rsp.data := readAtRsp.payload
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readAtCmd.valid := doRead
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readAtCmd.payload := 0
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def readAddress() : UInt = bus.cmd.address
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def writeAddress() : UInt = bus.cmd.address
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override def readHalt(): Unit = bus.cmd.ready := False
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override def writeHalt(): Unit = bus.cmd.ready := False
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override def build(): Unit = {
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super.doNonStopWrite(bus.cmd.data)
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def doMappedElements(jobs : Seq[BusSlaveFactoryElement]) = super.doMappedElements(
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jobs = jobs,
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askWrite = askWrite,
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askRead = askRead,
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doWrite = doWrite,
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doRead = doRead,
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writeData = bus.cmd.data,
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readData = readAtCmd.payload
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)
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switch(bus.cmd.address) {
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for ((address, jobs) <- elementsPerAddress if address.isInstanceOf[SingleMapping]) {
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is(address.asInstanceOf[SingleMapping].address) {
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doMappedElements(jobs)
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}
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}
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}
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for ((address, jobs) <- elementsPerAddress if !address.isInstanceOf[SingleMapping]) {
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when(address.hit(bus.cmd.address)){
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doMappedElements(jobs)
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}
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}
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}
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override def busDataWidth: Int = bus.config.dataWidth
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override def wordAddressInc: Int = busDataWidth / 8
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}
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case class SimpleBusDecoder(busConfig : SimpleBusConfig, mappings : Seq[AddressMapping], pendingMax : Int = 7) extends Component{
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val io = new Bundle {
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val input = slave(SimpleBus(busConfig))
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val outputs = Vec(master(SimpleBus(busConfig)), mappings.size)
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}
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val hits = Vec(Bool, mappings.size)
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for((slaveBus, memorySpace, hit) <- (io.outputs, mappings, hits).zipped) yield {
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hit := (memorySpace match {
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case DefaultMapping => !hits.filterNot(_ == hit).orR
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case _ => memorySpace.hit(io.input.cmd.address)
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})
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slaveBus.cmd.valid := io.input.cmd.valid && hit
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slaveBus.cmd.payload := io.input.cmd.payload.resized
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}
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val noHit = !hits.orR
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io.input.cmd.ready := (hits,io.outputs).zipped.map(_ && _.cmd.ready).orR || noHit
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val rspPendingCounter = Reg(UInt(log2Up(pendingMax + 1) bits)) init(0)
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rspPendingCounter := rspPendingCounter + U(io.input.cmd.fire && !io.input.cmd.wr) - U(io.input.rsp.valid)
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val rspHits = RegNextWhen(hits, io.input.cmd.fire)
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val rspPending = rspPendingCounter =/= 0
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val rspNoHit = !rspHits.orR
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io.input.rsp.valid := io.outputs.map(_.rsp.valid).orR || (rspPending && rspNoHit)
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io.input.rsp.payload := io.outputs.map(_.rsp.payload).read(OHToUInt(rspHits))
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val cmdWait = (io.input.cmd.valid && rspPending && hits =/= rspHits) || rspPendingCounter === pendingMax
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when(cmdWait){
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io.input.cmd.ready := False
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io.outputs.foreach(_.cmd.valid := False)
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}
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}
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object SimpleBusConnectors{
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def direct(m : SimpleBus, s : SimpleBus) : Unit = m >> s
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}
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case class SimpleBusInterconnect(){
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case class MasterModel(var connector : (SimpleBus,SimpleBus) => Unit = SimpleBusConnectors.direct)
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case class SlaveModel(mapping : AddressMapping, var connector : (SimpleBus,SimpleBus) => Unit = SimpleBusConnectors.direct)
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case class ConnectionModel(m : SimpleBus, s : SimpleBus, var connector : (SimpleBus,SimpleBus) => Unit = SimpleBusConnectors.direct)
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val masters = mutable.LinkedHashMap[SimpleBus, MasterModel]()
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val slaves = mutable.LinkedHashMap[SimpleBus, SlaveModel]()
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val connections = ArrayBuffer[ConnectionModel]()
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var pendingRspMax = 2
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def setConnector(bus : SimpleBus)( connector : (SimpleBus,SimpleBus) => Unit): Unit = (masters.get(bus), slaves.get(bus)) match {
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case (Some(m), _) => m.connector = connector
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case (None, Some(s)) => s.connector = connector
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}
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def setConnector(m : SimpleBus, s : SimpleBus)(connector : (SimpleBus,SimpleBus) => Unit): Unit = connections.find(e => e.m == m && e.s == s) match {
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case Some(c) => c.connector = connector
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}
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def addSlave(bus: SimpleBus,mapping: AddressMapping) : this.type = {
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slaves(bus) = SlaveModel(mapping)
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this
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}
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def addSlaves(orders : (SimpleBus,AddressMapping)*) : this.type = {
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orders.foreach(order => addSlave(order._1,order._2))
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this
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}
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def addMaster(bus : SimpleBus, accesses : Seq[SimpleBus]) : this.type = {
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masters(bus) = MasterModel()
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for(s <- accesses) connections += ConnectionModel(bus, s)
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this
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}
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def addMasters(specs : (SimpleBus,Seq[SimpleBus])*) : this.type = {
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specs.foreach(spec => addMaster(spec._1,spec._2))
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this
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}
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def build(): Unit ={
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def applyName(bus : Bundle,name : String, onThat : Nameable) : Unit = {
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if(bus.component == Component.current)
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onThat.setCompositeName(bus,name)
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else if(bus.isNamed)
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onThat.setCompositeName(bus.component,bus.getName() + "_" + name)
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}
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val connectionsInput = mutable.HashMap[ConnectionModel,SimpleBus]()
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val connectionsOutput = mutable.HashMap[ConnectionModel,SimpleBus]()
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for((bus, model) <- masters){
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val busConnections = connections.filter(_.m == bus)
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val busSlaves = busConnections.map(c => slaves(c.s))
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val decoder = new SimpleBusDecoder(bus.config, busSlaves.map(_.mapping))
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applyName(bus,"decoder",decoder)
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model.connector(bus, decoder.io.input)
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for((connection, decoderOutput) <- (busConnections, decoder.io.outputs).zipped) {
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connectionsInput(connection) = decoderOutput
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}
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}
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for((bus, model) <- slaves){
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val busConnections = connections.filter(_.s == bus)
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val busMasters = busConnections.map(c => masters(c.m))
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val arbiter = new SimpleBusArbiter(bus.config, busMasters.size, pendingRspMax)
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applyName(bus,"arbiter",arbiter)
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model.connector(arbiter.io.output, bus)
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for((connection, arbiterInput) <- (busConnections, arbiter.io.inputs).zipped) {
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connectionsOutput(connection) = arbiterInput
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}
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}
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for(connection <- connections){
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connection.connector(connectionsInput(connection), connectionsOutput(connection))
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}
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}
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//Will make SpinalHDL calling the build function at the end of the current component elaboration
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Component.current.addPrePopTask(build)
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}
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