Smaller and faster single stage instruction cache
Add fast two stage instruction cache Remove useless address == 0 checks in the HazardPlugin
This commit is contained in:
Charles Papon
parent
c83a157c64
commit
024e14ae58
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@ -128,7 +128,7 @@ class BranchPlugin(earlyBranch : Boolean,
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stages(indexOf(branchStage) - 1).arbitration.flushAll := True
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}
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if(catchAddressMisaligned) {
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if(catchAddressMisaligned) { //TODO conflict with instruction cache two stage
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branchExceptionPort.valid := arbitration.isValid && input(BRANCH_DO) && jumpInterface.payload(1 downto 0) =/= 0
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branchExceptionPort.code := 0
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branchExceptionPort.badAddr := jumpInterface.payload
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@ -180,7 +180,7 @@ class BranchPlugin(earlyBranch : Boolean,
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}
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if(catchAddressMisaligned) {
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predictionExceptionPort.valid := input(PREDICTION_HAD_BRANCHED) && arbitration.isValid && predictionJumpInterface.payload(1 downto 0) =/= 0
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predictionExceptionPort.valid := input(INSTRUCTION_READY) && input(PREDICTION_HAD_BRANCHED) && arbitration.isValid && predictionJumpInterface.payload(1 downto 0) =/= 0
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predictionExceptionPort.code := 0
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predictionExceptionPort.badAddr := predictionJumpInterface.payload
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}
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@ -236,7 +236,7 @@ class BranchPlugin(earlyBranch : Boolean,
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}
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if(catchAddressMisaligned) {
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branchExceptionPort.valid := arbitration.isValid && input(BRANCH_DO) && jumpInterface.payload(1 downto 0) =/= 0
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branchExceptionPort.valid := input(INSTRUCTION_READY) && arbitration.isValid && input(BRANCH_DO) && jumpInterface.payload(1 downto 0) =/= 0
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branchExceptionPort.code := 0
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branchExceptionPort.badAddr := jumpInterface.payload
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}
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@ -131,7 +131,7 @@ class DecoderSimplePlugin(catchIllegalInstruction : Boolean) extends Plugin[VexR
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if(catchIllegalInstruction){
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decodeExceptionPort.valid := arbitration.isValid && arbitration.haltIt && !input(LEGAL_INSTRUCTION) //HalitIt to alow decoder stage to wait valid data from 2 stages cache cache
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decodeExceptionPort.valid := arbitration.isValid && arbitration.haltIt && input(INSTRUCTION_READY) && !input(LEGAL_INSTRUCTION) //HalitIt to alow decoder stage to wait valid data from 2 stages cache cache
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decodeExceptionPort.code := 2
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decodeExceptionPort.badAddr.assignDontCare()
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}
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@ -82,12 +82,14 @@ class HazardSimplePlugin(bypassExecute : Boolean,
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trackHazardWithStage(execute ,bypassExecute ,BYPASSABLE_EXECUTE_STAGE)
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when(decode.input(INSTRUCTION)(rs1Range) === 0 || (if(pessimisticUseSrc) False else !decode.input(REG1_USE))){
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if(!pessimisticUseSrc) {
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when(!decode.input(REG1_USE)) {
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src0Hazard := False
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}
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when(decode.input(INSTRUCTION)(rs2Range) === 0 || (if(pessimisticUseSrc) False else !decode.input(REG2_USE))){
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when(!decode.input(REG2_USE)) {
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src1Hazard := False
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}
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}
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when(decode.arbitration.isValid && (src0Hazard || src1Hazard)){
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decode.arbitration.haltIt := True
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@ -61,6 +61,7 @@ class IBusCachedPlugin(config : InstructionCacheConfig) extends Plugin[VexRiscv]
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fetch.arbitration.haltIt setWhen (cache.io.cpu.fetch.haltIt)
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fetch.insert(INSTRUCTION) := cache.io.cpu.fetch.data
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decode.insert(INSTRUCTION_ANTICIPATED) := Mux(decode.arbitration.isStuck,decode.input(INSTRUCTION),fetch.output(INSTRUCTION))
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decode.insert(INSTRUCTION_READY) := True
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}
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cache.io.flush.cmd.valid := False
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@ -72,11 +73,13 @@ class IBusCachedPlugin(config : InstructionCacheConfig) extends Plugin[VexRiscv]
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cache.io.cpu.decode.address := decode.input(PC)
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decode.insert(INSTRUCTION) := cache.io.cpu.decode.data
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decode.insert(INSTRUCTION_ANTICIPATED) := cache.io.cpu.decode.dataAnticipated
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decode.insert(INSTRUCTION_READY) := !cache.io.cpu.decode.haltIt
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}
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if(catchAccessFault){
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if(!twoStageLogic) fetch.insert(IBUS_ACCESS_ERROR) := cache.io.cpu.fetch.error
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if( twoStageLogic) decode.insert(IBUS_ACCESS_ERROR) := cache.io.cpu.decode.error
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decodeExceptionPort.valid := decode.arbitration.isValid && decode.input(IBUS_ACCESS_ERROR)
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decodeExceptionPort.code := 1
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@ -105,7 +108,7 @@ case class InstructionCacheCpuFetch(p : InstructionCacheConfig) extends Bundle w
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val isStuck = Bool
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val isStuckByOthers = if(!p.twoStageLogic) Bool else null
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val address = UInt(p.addressWidth bit)
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val data = Bits(32 bit) //If twoStageLogic == true, this signal is acurate only when there is the cache doesn't stall decode (Used for Sync regfile)
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val data = if(!p.twoStageLogic) Bits(32 bit) else null
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val error = if(!p.twoStageLogic && p.catchAccessFault) Bool else null
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override def asMaster(): Unit = {
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@ -209,13 +212,26 @@ class InstructionCache(p : InstructionCacheConfig) extends Component{
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val lineRange = tagRange.low-1 downto log2Up(bytePerLine)
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val wordRange = log2Up(bytePerLine)-1 downto log2Up(bytePerWord)
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val tagLineRange = tagRange.high downto lineRange.low
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val lineWordRange = lineRange.high downto wordRange.low
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class LineInfo extends Bundle{
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val valid = Bool
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val loading = Bool
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val error = if(catchAccessFault) Bool else null
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val address = UInt(tagRange.length bit)
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}
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class LineInfoWithHit extends LineInfo{
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val hit = Bool
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}
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def LineInfoWithHit(lineInfo : LineInfo, testTag : UInt) = {
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val ret = new LineInfoWithHit()
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ret.assignSomeByName(lineInfo)
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ret.hit := lineInfo.valid && lineInfo.address === testTag
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ret
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}
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val ways = Array.fill(wayCount)(new Area{
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val tags = Mem(new LineInfo(),wayLineCount)
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@ -232,7 +248,6 @@ class InstructionCache(p : InstructionCacheConfig) extends Component{
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val flushCounter = Reg(UInt(log2Up(wayLineCount) + 1 bit)) init(0)
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when(!flushCounter.msb){
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io.cpu.prefetch.haltIt := True
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@ -260,10 +275,6 @@ class InstructionCache(p : InstructionCacheConfig) extends Component{
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val request = requestIn.stage()
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val lineInfoWrite = new LineInfo()
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lineInfoWrite.valid := flushCounter.msb
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lineInfoWrite.address := request.addr(tagRange)
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if(catchAccessFault) lineInfoWrite.error := loadingWithError
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//Send memory requests
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val memCmdSended = RegInit(False) setWhen(io.mem.cmd.fire)
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@ -279,10 +290,10 @@ class InstructionCache(p : InstructionCacheConfig) extends Component{
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val loadedWordsReadable = RegNext(loadedWords)
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loadedWordsNext := loadedWords
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val waysWritePort = ways(0).datas.writePort //Not multi ways
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waysWritePort.valid := io.mem.rsp.valid
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waysWritePort.address := request.addr(lineRange) @@ wordIndex
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waysWritePort.data := io.mem.rsp.data
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val waysDatasWritePort = ways(0).datas.writePort //Not multi ways
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waysDatasWritePort.valid := io.mem.rsp.valid
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waysDatasWritePort.address := request.addr(lineRange) @@ wordIndex
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waysDatasWritePort.data := io.mem.rsp.data
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when(io.mem.rsp.valid){
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wordIndex := wordIndex + 1
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loadedWordsNext(wordIndex) := True
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@ -297,11 +308,14 @@ class InstructionCache(p : InstructionCacheConfig) extends Component{
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}
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request.ready := readyDelay === 1
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val waysTagsWritePort = ways(0).tags.writePort //not multi way
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waysTagsWritePort.valid := io.mem.rsp.valid || !flushCounter.msb
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waysTagsWritePort.address := Mux(flushCounter.msb,request.addr(lineRange),flushCounter(flushCounter.high-1 downto 0))
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waysTagsWritePort.data.valid := flushCounter.msb
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waysTagsWritePort.data.address := request.addr(tagRange)
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waysTagsWritePort.data.loading := !memRspLast
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if(catchAccessFault) waysTagsWritePort.data.error := loadingWithError
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when((request.valid && memRspLast) || !flushCounter.msb){
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val tagsAddress = Mux(flushCounter.msb,request.addr(lineRange),flushCounter(flushCounter.high-1 downto 0))
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ways(0).tags(tagsAddress) := lineInfoWrite //TODO
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}
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when(requestIn.ready){
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memCmdSended := False
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@ -321,9 +335,9 @@ class InstructionCache(p : InstructionCacheConfig) extends Component{
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val waysRead = for(way <- ways) yield new Area{
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val readAddress = Mux(io.cpu.fetch.isStuck,io.cpu.fetch.address,io.cpu.prefetch.address) //TODO FMAX
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val tag = if(asyncTagMemory)
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way.tags.readAsync(io.cpu.fetch.address(lineRange))
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way.tags.readAsync(io.cpu.fetch.address(lineRange),writeFirst)
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else
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way.tags.readSync(readAddress(lineRange))
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way.tags.readSync(readAddress(lineRange),readUnderWrite = readFirst)
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val data = way.datas.readSync(readAddress(lineRange.high downto wordRange.low))
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waysHitWord := data //Not applicable to multi way
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@ -332,102 +346,128 @@ class InstructionCache(p : InstructionCacheConfig) extends Component{
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if(catchAccessFault) waysHitError := tag.error
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}
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when(lineLoader.request.valid && lineLoader.request.addr(lineRange) === io.cpu.fetch.address(lineRange)){
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waysHitValid := False //Not applicable to multi way
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}
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// when(lineLoader.request.valid && lineLoader.request.addr(lineRange) === io.cpu.fetch.address(lineRange)){
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// waysHitValid := False //Not applicable to multi way
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// }
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}
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val loaderHitValid = lineLoader.request.valid && lineLoader.request.addr(tagLineRange) === io.cpu.fetch.address(tagLineRange)
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val loaderHitReady = lineLoader.loadedWordsReadable(io.cpu.fetch.address(wordRange))
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io.cpu.fetch.haltIt := io.cpu.fetch.isValid && !(waysHitValid || (loaderHitValid && loaderHitReady))
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io.cpu.fetch.data := waysHitWord //TODO
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if(catchAccessFault) io.cpu.fetch.error := (waysHitValid && waysHitError) || (loaderHitValid && loaderHitReady && lineLoader.loadingWithErrorReg)
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lineLoader.requestIn.valid := io.cpu.fetch.isValid && !io.cpu.fetch.isStuckByOthers && !waysHitValid
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val hit = waysHitValid && !(waysRead(0).tag.loading && !(if(asyncTagMemory) lineLoader.loadedWords else RegNext(lineLoader.loadedWords))(io.cpu.fetch.address(wordRange)))
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io.cpu.fetch.haltIt := io.cpu.fetch.isValid && !hit
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io.cpu.fetch.data := waysHitWord
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if(catchAccessFault) io.cpu.fetch.error := waysRead(0).tag.error
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lineLoader.requestIn.valid := io.cpu.fetch.isValid && !hit //TODO avoid duplicated request
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lineLoader.requestIn.addr := io.cpu.fetch.address
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// val loaderHitValid = lineLoader.request.valid && lineLoader.request.addr(tagLineRange) === io.cpu.fetch.address(tagLineRange)
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// val loaderHitReady = lineLoader.loadedWordsReadable(io.cpu.fetch.address(wordRange))
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//
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//
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// io.cpu.fetch.haltIt := io.cpu.fetch.isValid && !(waysHitValid || (loaderHitValid && loaderHitReady))
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// io.cpu.fetch.data := waysHitWord //TODO
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// if(catchAccessFault) io.cpu.fetch.error := (waysHitValid && waysHitError) || (loaderHitValid && loaderHitReady && lineLoader.loadingWithErrorReg)
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// lineLoader.requestIn.valid := io.cpu.fetch.isValid && !io.cpu.fetch.isStuckByOthers && !waysHitValid
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// lineLoader.requestIn.addr := io.cpu.fetch.address
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} else new Area{
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val waysHitValid = False
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val waysHitError = Bool.assignDontCare()
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val waysHitWord = Bits(wordWidth bit)
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//Long readValidPath
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// def writeFirstMemWrap[T <: Data](readValid : Bool, readAddress : UInt, lastAddress : UInt, readData : T,writeValid : Bool, writeAddress : UInt, writeData : T) : T = {
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// val hit = writeValid && (readValid ? readAddress | lastAddress) === writeAddress
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// val overrideValid = RegInit(False) clearWhen(readValid) setWhen(hit)
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// val overrideValue = RegNextWhen(writeData,hit)
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// overrideValid ? overrideValue | readData
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// }
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val waysRead = for(way <- ways) yield new Area{
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//shot readValid path
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def writeFirstMemWrap[T <: Data](readValid : Bool, readLastAddress : UInt, readData : T,writeValid : Bool, writeAddress : UInt, writeData : T) : T = {
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val writeSample = readValid || (writeValid && writeAddress === readLastAddress)
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val writeValidReg = RegNextWhen(writeValid,writeSample)
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val writeAddressReg = RegNextWhen(writeAddress,writeSample)
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val writeDataReg = RegNextWhen(writeData,writeSample)
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(writeValidReg && writeAddressReg === readLastAddress) ? writeDataReg | readData
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}
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//Long sample path
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// def writeFirstRegWrap[T <: Data](sample : Bool, sampleAddress : UInt,lastAddress : UInt, readData : T, writeValid : Bool, writeAddress : UInt, writeData : T) : (T,T) = {
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// val hit = writeValid && (sample ? sampleAddress | lastAddress) === writeAddress
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// val bypass = hit ? writeData | readData
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// val reg = RegNextWhen(bypass,sample || hit)
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// (reg,bypass)
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// }
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//Short sample path
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def writeFirstRegWrap[T <: Data](sample : Bool, sampleAddress : UInt,sampleLastAddress : UInt, readData : T, writeValid : Bool, writeAddress : UInt, writeData : T) = {
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val preWrite = (writeValid && sampleAddress === writeAddress)
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val postWrite = (writeValid && sampleLastAddress === writeAddress)
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val bypass = (!sample || preWrite) ? writeData | readData
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val regEn = sample || postWrite
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val reg = RegNextWhen(bypass,regEn)
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(reg,bypass,regEn,preWrite,postWrite)
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}
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// def writeFirstRegWrap[T <: Data](sample : Bool, sampleAddress : UInt,sampleLastAddress : UInt, readData : T, writeValid : Bool, writeAddress : UInt, writeData : T) = {
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// val bypass = (!sample || (writeValid && sampleAddress === writeAddress)) ? writeData | readData
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// val regEn = sample || (writeValid && sampleLastAddress === writeAddress)
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// val reg = RegNextWhen(bypass,regEn)
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// (reg,bypass,regEn,False,False)
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// }
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require(wayCount == 1)
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val memRead = new Area{
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val way = ways(0)
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val tag = if(asyncTagMemory)
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way.tags.readAsync(io.cpu.fetch.address(lineRange))
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way.tags.readAsync(io.cpu.fetch.address(lineRange),writeFirst)
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else
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way.tags.readSync(io.cpu.prefetch.address(lineRange),enable = !io.cpu.fetch.isStuck)
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writeFirstMemWrap(
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readValid = !io.cpu.fetch.isStuck,
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// readAddress = io.cpu.prefetch.address(lineRange),
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readLastAddress = io.cpu.fetch.address(lineRange),
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readData = way.tags.readSync(io.cpu.prefetch.address(lineRange),enable = !io.cpu.fetch.isStuck),
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writeValid = lineLoader.waysTagsWritePort.valid,
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writeAddress = lineLoader.waysTagsWritePort.address,
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writeData = lineLoader.waysTagsWritePort.data
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)
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val data = way.datas.readSync(io.cpu.prefetch.address(lineRange.high downto wordRange.low),enable = !io.cpu.fetch.isStuck)
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waysHitWord := data //Not applicable to multi way
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when(tag.valid && tag.address === io.cpu.fetch.address(tagRange)) {
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waysHitValid := True
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if(catchAccessFault) waysHitError := tag.error
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}
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when(lineLoader.request.valid && lineLoader.request.addr(lineRange) === io.cpu.fetch.address(lineRange)){
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waysHitValid := False //Not applicable to multi way
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}
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val data = writeFirstMemWrap(
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readValid = !io.cpu.fetch.isStuck,
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// readAddress = io.cpu.prefetch.address(lineWordRange),
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readLastAddress = io.cpu.fetch.address(lineWordRange),
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readData = way.datas.readSync(io.cpu.prefetch.address(lineWordRange),enable = !io.cpu.fetch.isStuck),
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writeValid = lineLoader.waysDatasWritePort.valid,
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writeAddress = lineLoader.waysDatasWritePort.address,
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writeData = lineLoader.waysDatasWritePort.data
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)
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}
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val tag = writeFirstRegWrap(
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sample = !io.cpu.decode.isStuck,
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sampleAddress = io.cpu.fetch.address(lineRange),
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sampleLastAddress = io.cpu.decode.address(lineRange),
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readData = LineInfoWithHit(memRead.tag,io.cpu.fetch.address(tagRange)),
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writeValid = lineLoader.waysTagsWritePort.valid,
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writeAddress = lineLoader.waysTagsWritePort.address,
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writeData = LineInfoWithHit(lineLoader.waysTagsWritePort.data,io.cpu.fetch.address(tagRange)) //TODO wrong address src
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)._1
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val loadedWord = new Area{
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val valid = RegNext(lineLoader.waysWritePort.valid)
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val address = RegNext(lineLoader.request.addr(tagLineRange) @@ lineLoader.wordIndex @@ U"00")
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val data = RegNext(lineLoader.waysWritePort.data)
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val wasLoaded = RegNext(lineLoader.loadedWords)
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}
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val (data,dataRegIn,dataRegEn,dataPreWrite,dataPostWrite) = writeFirstRegWrap(
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sample = !io.cpu.decode.isStuck,
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sampleAddress = io.cpu.fetch.address(lineWordRange),
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sampleLastAddress = io.cpu.decode.address(lineWordRange),
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readData = memRead.data,
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writeValid = lineLoader.waysDatasWritePort.valid,
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writeAddress = lineLoader.waysDatasWritePort.address,
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writeData = lineLoader.waysDatasWritePort.data
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)
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val hit = tag.valid && tag.address === io.cpu.decode.address(tagRange) && !(tag.loading && !lineLoader.loadedWords(io.cpu.decode.address(wordRange)))
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// val hit = tag.hit && !(tag.loading && !lineLoader.loadedWords(io.cpu.decode.address(wordRange)))
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val fetchInstructionValid = Bool
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val fetchInstructionValue = Bits(32 bits)
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val fetchInstructionValidReg = Reg(Bool)
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val fetchInstructionValueReg = Reg(Bits(32 bits))
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io.cpu.decode.haltIt := io.cpu.decode.isValid && !hit //TODO PERF not halit it when removed, Should probably be applyed in many other places
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io.cpu.decode.data := data
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// io.cpu.decode.dataAnticipated := dataRegEn ? dataRegIn | data
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io.cpu.decode.dataAnticipated := io.cpu.decode.isStuck ? Mux(dataPostWrite,lineLoader.waysDatasWritePort.data,data) | Mux(dataPreWrite,lineLoader.waysDatasWritePort.data,memRead.data)
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if(catchAccessFault) io.cpu.decode.error := tag.error
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when(fetchInstructionValidReg){
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fetchInstructionValid := True
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fetchInstructionValue := fetchInstructionValueReg
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}.elsewhen(loadedWord.valid && (loadedWord.address >> 2) === (io.cpu.fetch.address >> 2)){
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fetchInstructionValid := True
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fetchInstructionValue := loadedWord.data
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} otherwise{
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fetchInstructionValid := waysHitValid || (loadedWord.address(tagLineRange) === io.cpu.fetch.address(tagLineRange) && loadedWord.wasLoaded(io.cpu.fetch.address(wordRange)))
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fetchInstructionValue := waysHitWord //Not multi way (wasloaded)
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}
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when(io.cpu.fetch.isStuck){
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fetchInstructionValidReg := fetchInstructionValid
|
||||
fetchInstructionValueReg := fetchInstructionValue
|
||||
} otherwise {
|
||||
fetchInstructionValidReg := False
|
||||
}
|
||||
|
||||
io.cpu.fetch.data := fetchInstructionValue
|
||||
|
||||
|
||||
val decodeInstructionValid = Reg(Bool)
|
||||
val decodeInstructionReg = Reg(Bits(32 bits))
|
||||
val decodeInstructionRegIn = (!io.cpu.decode.isStuck) ? fetchInstructionValue | loadedWord.data
|
||||
|
||||
io.cpu.decode.dataAnticipated := decodeInstructionReg
|
||||
when(!io.cpu.decode.isStuck){
|
||||
decodeInstructionValid := fetchInstructionValid
|
||||
decodeInstructionReg := decodeInstructionRegIn
|
||||
io.cpu.decode.dataAnticipated := decodeInstructionRegIn
|
||||
}.elsewhen(loadedWord.valid && (loadedWord.address >> 2) === (io.cpu.decode.address >> 2)){
|
||||
decodeInstructionValid := True
|
||||
decodeInstructionReg := decodeInstructionRegIn
|
||||
io.cpu.decode.dataAnticipated := decodeInstructionRegIn
|
||||
}
|
||||
|
||||
io.cpu.decode.haltIt := io.cpu.decode.isValid && !decodeInstructionValid
|
||||
io.cpu.decode.data := decodeInstructionReg
|
||||
|
||||
|
||||
lineLoader.requestIn.valid := io.cpu.decode.isValid && !decodeInstructionValid
|
||||
lineLoader.requestIn.valid := io.cpu.decode.isValid && !hit //TODO avoid duplicated request
|
||||
lineLoader.requestIn.addr := io.cpu.decode.address
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -61,6 +61,7 @@ class IBusSimplePlugin(interfaceKeepData : Boolean, catchAccessFault : Boolean)
|
|||
fetch.insert(IBUS_ACCESS_ERROR) := iBus.rsp.error
|
||||
fetch.arbitration.haltIt setWhen(fetch.arbitration.isValid && !iBus.rsp.ready)
|
||||
decode.insert(INSTRUCTION_ANTICIPATED) := Mux(decode.arbitration.isStuck,decode.input(INSTRUCTION),fetch.output(INSTRUCTION))
|
||||
decode.insert(INSTRUCTION_READY) := True
|
||||
|
||||
if(catchAccessFault){
|
||||
decodeExceptionPort.valid := decode.arbitration.isValid && decode.input(IBUS_ACCESS_ERROR)
|
||||
|
|
|
|||
|
|
@ -79,22 +79,24 @@ object TopLevel {
|
|||
|
||||
configFull.plugins ++= List(
|
||||
new PcManagerSimplePlugin(0x00000000l, false),
|
||||
new IBusSimplePlugin(
|
||||
interfaceKeepData = true,
|
||||
catchAccessFault = true
|
||||
),
|
||||
// new IBusCachedPlugin(
|
||||
// config = InstructionCacheConfig(
|
||||
// cacheSize =4096,
|
||||
// bytePerLine =32,
|
||||
// wayCount = 1,
|
||||
// wrappedMemAccess = true,
|
||||
// addressWidth = 32,
|
||||
// cpuDataWidth = 32,
|
||||
// memDataWidth = 32,
|
||||
// new IBusSimplePlugin(
|
||||
// interfaceKeepData = true,
|
||||
// catchAccessFault = true
|
||||
// )
|
||||
// ),
|
||||
new IBusCachedPlugin(
|
||||
config = InstructionCacheConfig(
|
||||
cacheSize = 4096,
|
||||
bytePerLine =32,
|
||||
wayCount = 1,
|
||||
wrappedMemAccess = true,
|
||||
addressWidth = 32,
|
||||
cpuDataWidth = 32,
|
||||
memDataWidth = 32,
|
||||
catchAccessFault = true,
|
||||
asyncTagMemory = false,
|
||||
twoStageLogic = true
|
||||
)
|
||||
),
|
||||
new DBusSimplePlugin(
|
||||
catchAddressMisaligned = true,
|
||||
catchAccessFault = true
|
||||
|
|
@ -269,9 +271,9 @@ object TopLevel {
|
|||
)
|
||||
)
|
||||
|
||||
// val toplevel = new VexRiscv(configFull)
|
||||
val toplevel = new VexRiscv(configFull)
|
||||
// val toplevel = new VexRiscv(configLight)
|
||||
val toplevel = new VexRiscv(configTest)
|
||||
// val toplevel = new VexRiscv(configTest)
|
||||
toplevel.decode.input(toplevel.config.INSTRUCTION).addAttribute(Verilator.public)
|
||||
toplevel.decode.input(toplevel.config.PC).addAttribute(Verilator.public)
|
||||
toplevel.decode.arbitration.isValid.addAttribute(Verilator.public)
|
||||
|
|
|
|||
|
|
@ -19,6 +19,7 @@ case class VexRiscvConfig(pcWidth : Int){
|
|||
object PC extends Stageable(UInt(pcWidth bits))
|
||||
object PC_CALC_WITHOUT_JUMP extends Stageable(UInt(pcWidth bits))
|
||||
object INSTRUCTION extends Stageable(Bits(32 bits))
|
||||
object INSTRUCTION_READY extends Stageable(Bool)
|
||||
object INSTRUCTION_ANTICIPATED extends Stageable(Bits(32 bits))
|
||||
object LEGAL_INSTRUCTION extends Stageable(Bool)
|
||||
object REGFILE_WRITE_VALID extends Stageable(Bool)
|
||||
|
|
|
|||
|
|
@ -1,52 +1,66 @@
|
|||
[*]
|
||||
[*] GTKWave Analyzer v3.3.58 (w)1999-2014 BSI
|
||||
[*] Sun Apr 9 09:10:08 2017
|
||||
[*] Wed Apr 12 17:13:59 2017
|
||||
[*]
|
||||
[dumpfile] "/home/spinalvm/Spinal/VexRiscv/src/test/cpp/testA/rv32ui-p-addi.vcd"
|
||||
[dumpfile_mtime] "Sun Apr 9 09:08:48 2017"
|
||||
[dumpfile_size] 136439
|
||||
[dumpfile] "/home/spinalvm/Spinal/VexRiscv/src/test/cpp/testA/dhrystoneO3.vcd"
|
||||
[dumpfile_mtime] "Wed Apr 12 17:05:50 2017"
|
||||
[dumpfile_size] 476292557
|
||||
[savefile] "/home/spinalvm/Spinal/VexRiscv/src/test/cpp/testA/fail.gtkw"
|
||||
[timestart] 274
|
||||
[timestart] 602234
|
||||
[size] 1776 953
|
||||
[pos] -775 -353
|
||||
*-2.774728 284 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
|
||||
[pos] -775 -1
|
||||
*-3.626630 602285 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
|
||||
[treeopen] TOP.
|
||||
[treeopen] TOP.VexRiscv.
|
||||
[sst_width] 201
|
||||
[signals_width] 453
|
||||
[signals_width] 518
|
||||
[sst_expanded] 1
|
||||
[sst_vpaned_height] 279
|
||||
@800200
|
||||
-prefetch
|
||||
@28
|
||||
TOP.VexRiscv.instructionCache_1.io_cpu_prefetch_haltIt
|
||||
@22
|
||||
TOP.VexRiscv.instructionCache_1.io_cpu_prefetch_address[31:0]
|
||||
@1000200
|
||||
-prefetch
|
||||
@800200
|
||||
-fetch
|
||||
@28
|
||||
TOP.VexRiscv.instructionCache_1.io_cpu_fetch_isValid
|
||||
TOP.VexRiscv.instructionCache_1.io_cpu_fetch_isStuck
|
||||
TOP.VexRiscv.instructionCache_1.io_cpu_prefetch_haltIt
|
||||
@800200
|
||||
-Fetch
|
||||
@22
|
||||
TOP.VexRiscv.instructionCache_1.io_cpu_fetch_address[31:0]
|
||||
TOP.VexRiscv.instructionCache_1.io_cpu_fetch_data[31:0]
|
||||
@1000200
|
||||
-fetch
|
||||
@800200
|
||||
-decode
|
||||
@28
|
||||
TOP.VexRiscv.instructionCache_1.io_cpu_decode_isValid
|
||||
TOP.VexRiscv.instructionCache_1.io_cpu_decode_haltIt
|
||||
TOP.VexRiscv.instructionCache_1.io_cpu_decode_isStuck
|
||||
TOP.VexRiscv.instructionCache_1.io_cpu_fetch_isStuck
|
||||
TOP.VexRiscv.instructionCache_1.io_cpu_fetch_isValid
|
||||
@1000200
|
||||
-Fetch
|
||||
@800200
|
||||
-Decode
|
||||
@22
|
||||
TOP.VexRiscv.instructionCache_1.io_cpu_decode_address[31:0]
|
||||
TOP.VexRiscv.instructionCache_1.io_cpu_decode_data[31:0]
|
||||
@28
|
||||
TOP.VexRiscv.instructionCache_1.io_cpu_decode_haltIt
|
||||
TOP.VexRiscv.instructionCache_1.io_cpu_decode_isStuck
|
||||
TOP.VexRiscv.instructionCache_1.io_cpu_decode_isValid
|
||||
@1000200
|
||||
-decode
|
||||
-Decode
|
||||
@800200
|
||||
-ibus
|
||||
-Task
|
||||
@22
|
||||
TOP.VexRiscv.instructionCache_1.task_memRead_data[31:0]
|
||||
TOP.VexRiscv.instructionCache_1.task_memRead_tag_address[19:0]
|
||||
@28
|
||||
TOP.VexRiscv.instructionCache_1.task_memRead_tag_valid
|
||||
@22
|
||||
TOP.VexRiscv.instructionCache_1.task_tag_address[19:0]
|
||||
@28
|
||||
TOP.VexRiscv.instructionCache_1.task_tag_valid
|
||||
@22
|
||||
TOP.VexRiscv.instructionCache_1.task_dataRegIn[31:0]
|
||||
TOP.VexRiscv.instructionCache_1.task_data[31:0]
|
||||
@29
|
||||
TOP.VexRiscv.instructionCache_1.task_cacheHit
|
||||
@28
|
||||
TOP.VexRiscv.instructionCache_1.task_hit
|
||||
TOP.VexRiscv.instructionCache_1.task_loaderHit
|
||||
@1000200
|
||||
-Task
|
||||
@22
|
||||
TOP.VexRiscv.instructionCache_1.io_mem_cmd_payload_address[31:0]
|
||||
@28
|
||||
|
|
@ -56,32 +70,16 @@ TOP.VexRiscv.instructionCache_1.io_mem_cmd_valid
|
|||
TOP.VexRiscv.instructionCache_1.io_mem_rsp_payload_data[31:0]
|
||||
@28
|
||||
TOP.VexRiscv.instructionCache_1.io_mem_rsp_valid
|
||||
@1000200
|
||||
-ibus
|
||||
@28
|
||||
TOP.VexRiscv.instructionCache_1.clk
|
||||
@22
|
||||
TOP.VexRiscv.instructionCache_1.io_cpu_fetch_data[31:0]
|
||||
TOP.VexRiscv.decode_RegFilePlugin_srcInstruction[31:0]
|
||||
TOP.VexRiscv.instructionCache_1.io_cpu_decode_data[31:0]
|
||||
@29
|
||||
TOP.VexRiscv.decode_arbitration_isValid
|
||||
TOP.VexRiscv.instructionCache_1.lineLoader_waysDatasWritePort_payload_address[9:0]
|
||||
TOP.VexRiscv.instructionCache_1.lineLoader_waysDatasWritePort_payload_data[31:0]
|
||||
@28
|
||||
TOP.VexRiscv.decode_arbitration_isStuck
|
||||
TOP.VexRiscv.instructionCache_1.lineLoader_waysDatasWritePort_valid
|
||||
TOP.VexRiscv.clk
|
||||
@22
|
||||
TOP.VexRiscv.decode_PC[31:0]
|
||||
TOP.VexRiscv.decode_REG1[31:0]
|
||||
TOP.VexRiscv.decode_REG2[31:0]
|
||||
TOP.VexRiscv.instructionCache_1.lineLoader_request_payload_addr[31:0]
|
||||
@28
|
||||
TOP.VexRiscv.decode_REG1_USE
|
||||
TOP.VexRiscv.decode_REG2_USE
|
||||
TOP.VexRiscv.decode_arbitration_isValid
|
||||
TOP.VexRiscv.decode_arbitration_isStuck
|
||||
@22
|
||||
TOP.VexRiscv.decode_RegFilePlugin_regFileReadAddress1[4:0]
|
||||
TOP.VexRiscv.decode_RegFilePlugin_regFileReadAddress2[4:0]
|
||||
TOP.VexRiscv.decode_RegFilePlugin_rs1Data[31:0]
|
||||
TOP.VexRiscv.decode_RegFilePlugin_rs2Data[31:0]
|
||||
TOP.VexRiscv.decode_RegFilePlugin_srcInstruction[31:0]
|
||||
TOP.VexRiscv.instructionCache_1.lineLoader_request_ready
|
||||
TOP.VexRiscv.instructionCache_1.lineLoader_request_valid
|
||||
[pattern_trace] 1
|
||||
[pattern_trace] 0
|
||||
|
|
|
|||
|
|
@ -681,11 +681,12 @@ public:
|
|||
#endif
|
||||
class Dhrystone : public Workspace{
|
||||
public:
|
||||
|
||||
Dhrystone(string name,bool iStall, bool dStall) : Workspace(name) {
|
||||
string hexName;
|
||||
Dhrystone(string name,string hexName,bool iStall, bool dStall) : Workspace(name) {
|
||||
setIStall(iStall);
|
||||
setDStall(dStall);
|
||||
loadHex("../../resources/hex/" + name + ".hex");
|
||||
loadHex("../../resources/hex/" + hexName + ".hex");
|
||||
this->hexName = hexName;
|
||||
}
|
||||
|
||||
virtual void checks(){
|
||||
|
|
@ -693,7 +694,7 @@ public:
|
|||
}
|
||||
|
||||
virtual void pass(){
|
||||
FILE *refFile = fopen((name + ".logRef").c_str(), "r");
|
||||
FILE *refFile = fopen((hexName + ".logRef").c_str(), "r");
|
||||
fseek(refFile, 0, SEEK_END);
|
||||
uint32_t refSize = ftell(refFile);
|
||||
fseek(refFile, 0, SEEK_SET);
|
||||
|
|
@ -828,10 +829,10 @@ int main(int argc, char **argv, char **env) {
|
|||
#ifdef DHRYSTONE
|
||||
// Dhrystone("dhrystoneO3",false,false).run(0.05e6);
|
||||
|
||||
Dhrystone("dhrystoneO3",true,true).run(1.1e6);
|
||||
Dhrystone("dhrystoneO3M",true,true).run(1.5e6);
|
||||
Dhrystone("dhrystoneO3",false,false).run(1.5e6);
|
||||
Dhrystone("dhrystoneO3M",false,false).run(1.2e6);
|
||||
Dhrystone("dhrystoneO3_Stall","dhrystoneO3",true,true).run(1.1e6);
|
||||
Dhrystone("dhrystoneO3M_Stall","dhrystoneO3M",true,true).run(1.5e6);
|
||||
Dhrystone("dhrystoneO3","dhrystoneO3",false,false).run(1.5e6);
|
||||
Dhrystone("dhrystoneO3M","dhrystoneO3M",false,false).run(1.2e6);
|
||||
|
||||
// Dhrystone("dhrystoneO3ML",false,false).run(8e6);
|
||||
// Dhrystone("dhrystoneO3MLL",false,false).run(80e6);
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
IBUS=IBUS_SIMPLE
|
||||
IBUS=IBUS_CACHED
|
||||
DBUS=DBUS_SIMPLE
|
||||
TRACE=no
|
||||
TRACE_START=0
|
||||
|
|
|
|||
Loading…
Reference in New Issue