Hardware/VexRiscv
1
0
Fork 0
mirror of https://github.com/SpinalHDL/VexRiscv.git synced 2025-01-03 03:43:39 -05:00
Code Issues Projects Releases Packages Wiki Activity

typo

Browse source
This commit is contained in:
Dolu1990 2020-03-01 13:03:40 +01:00
parent 559260020b
commit 02545b9bea
1 changed files with 1 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
README.md
View file

@ -186,7 +186,7 @@ NOTES:
[![Build Status](https://travis-ci.org/SpinalHDL/VexRiscv.svg?branch=master)](https://travis-ci.org/SpinalHDL/VexRiscv)
To run tests (need the java, scala, verilator), just do :
To run tests (need java, scala, verilator), just do :
```sh
export VEXRISCV_REGRESSION_SEED=42