Hardware
/
VexRiscv
mirror of https://github.com/SpinalHDL/VexRiscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Fix dBusSimplePlugin to bmb bridge

This commit is contained in:
Charles Papon 2019-05-16 19:49:13 +02:00
parent 4ce9d805b4
commit 0301ced000
1 changed files with 8 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala
View File

@ -259,11 +259,17 @@ case class DBusSimpleBus() extends Bundle with IMasterSlave{
bus.cmd.opcode := (cmd.wr ? B(Bmb.Cmd.Opcode.WRITE) | B(Bmb.Cmd.Opcode.READ))
bus.cmd.address := cmd.address.resized
bus.cmd.data := cmd.data
bus.cmd.length := cmd.size.mux(
0 -> U"00",
1 -> U"01",
default -> U"11"
)
bus.cmd.mask := cmd.size.mux(
0 -> B"0001",
1 -> B"0011",
default -> B"1111"
) |<< cmd.address(1 downto 0)
cmd.ready := bus.cmd.ready
rsp.ready := bus.rsp.valid && !bus.rsp.context(0)