Hardware
/
VexRiscv
mirror of https://github.com/SpinalHDL/VexRiscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

More Unrolls

This commit is contained in:
Tom Verbeure 2018-05-28 07:20:26 +00:00
parent 1613191779
commit 0335543309
1 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/main/scala/vexriscv/TestsWorkspace.scala
View File

@ -117,8 +117,8 @@ object TestsWorkspace {
new MulDivIterativePlugin( new MulDivIterativePlugin(
genMul = true, genMul = true,
genDiv = true, genDiv = true,
mulUnroolFactor = 32, mulUnrollFactor = 32,
divUnroolFactor = 1 divUnrollFactor = 1
), ),
// new DivPlugin, // new DivPlugin,
new CsrPlugin(CsrPluginConfig.all(0x80000020l).copy(deterministicInteruptionEntry = false)), new CsrPlugin(CsrPluginConfig.all(0x80000020l).copy(deterministicInteruptionEntry = false)),
@ -298,4 +298,4 @@ object TestsWorkspace {
//TODO MulPlugin doesn't fit well on Artix (FMAX) //TODO MulPlugin doesn't fit well on Artix (FMAX)
//TODO PcReg design is unoptimized by Artix synthesis //TODO PcReg design is unoptimized by Artix synthesis
//TODO FMAX SRC mux + bipass mux prioriti //TODO FMAX SRC mux + bipass mux prioriti
//TODO FMAX, isFiring is to pesimisstinc in some cases(include removeIt flushed ..) //TODO FMAX, isFiring is to pesimisstinc in some cases(include removeIt flushed ..)