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Fix SMP for configuration without writeback stage.

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Include SMP core into the single core tests regressions
This commit is contained in:
Dolu1990 2020-04-28 15:50:20 +02:00
parent 4a49b23636
commit 03a0445775
2 changed files with 11 additions and 7 deletions
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4
src/main/scala/vexriscv/ip/DataCache.scala
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@ -565,8 +565,8 @@ class DataCache(val p : DataCacheConfig) extends Component{
//Ensure write to read consistency
val consistancyCheck = (withInvalidate || withWriteResponse) generate new Area {
val fenceConsistent = (if(withInvalidate) sync.fenceConsistent else pending.done) && !io.cpu.writeBack.fenceValid && !io.cpu.memory.fenceValid //Pessimistic fence tracking
val totalyConsistent = (if(withInvalidate) sync.totalyConsistent else pending.done) && !(io.cpu.memory.isValid && io.cpu.memory.isWrite) && !(io.cpu.writeBack.isValid && io.cpu.memory.isWrite)
val fenceConsistent = (if(withInvalidate) sync.fenceConsistent else pending.done) && !io.cpu.writeBack.fenceValid && (if(mergeExecuteMemory) True else !io.cpu.memory.fenceValid) //Pessimistic fence tracking
val totalyConsistent = (if(withInvalidate) sync.totalyConsistent else pending.done) && (if(mergeExecuteMemory) True else !(io.cpu.memory.isValid && io.cpu.memory.isWrite)) && !(io.cpu.writeBack.isValid && io.cpu.memory.isWrite)
when(io.cpu.execute.isValid /*&& (!io.cpu.execute.args.wr || isAmo)*/){
when(!fenceConsistent || io.cpu.execute.totalyConsistent && !totalyConsistent){
io.cpu.execute.haltIt := True

14
src/test/scala/vexriscv/TestIndividualFeatures.scala
View file

@ -427,8 +427,10 @@ class DBusDimension extends VexRiscvDimension("DBus") {
var cacheSize = 0
var wayCount = 0
val withLrSc = catchAll
val withAmo = catchAll && r.nextBoolean()
val dBusRspSlavePipe, relaxedMemoryTranslationRegister = r.nextBoolean()
val withSmp = withLrSc && r.nextBoolean()
val withAmo = catchAll && r.nextBoolean() || withSmp
val dBusRspSlavePipe = r.nextBoolean() || withSmp
val relaxedMemoryTranslationRegister = r.nextBoolean()
val earlyWaysHits = r.nextBoolean() && !noWriteBack
val dBusCmdMasterPipe, dBusCmdSlavePipe = false //As it create test bench issues
@ -436,8 +438,8 @@ class DBusDimension extends VexRiscvDimension("DBus") {
cacheSize = 512 << r.nextInt(5)
wayCount = 1 << r.nextInt(3)
}while(cacheSize/wayCount < 512 || (catchAll && cacheSize/wayCount > 4096))
new VexRiscvPosition("Cached" + "S" + cacheSize + "W" + wayCount + "BPL" + bytePerLine + (if(dBusCmdMasterPipe) "Cmp " else "") + (if(dBusCmdSlavePipe) "Csp " else "") + (if(dBusRspSlavePipe) "Rsp " else "") + (if(relaxedMemoryTranslationRegister) "Rmtr " else "") + (if(earlyWaysHits) "Ewh " else "") + (if(withAmo) "Amo " else "")) {
override def testParam = "DBUS=CACHED " + (if(withLrSc) "LRSC=yes " else "") + (if(withAmo) "AMO=yes " else "")
new VexRiscvPosition("Cached" + "S" + cacheSize + "W" + wayCount + "BPL" + bytePerLine + (if(dBusCmdMasterPipe) "Cmp " else "") + (if(dBusCmdSlavePipe) "Csp " else "") + (if(dBusRspSlavePipe) "Rsp " else "") + (if(relaxedMemoryTranslationRegister) "Rmtr " else "") + (if(earlyWaysHits) "Ewh " else "") + (if(withAmo) "Amo " else "") + (if(withSmp) "Smp " else "")) {
override def testParam = "DBUS=CACHED " + (if(withLrSc) "LRSC=yes " else "") + (if(withAmo) "AMO=yes " else "") + (if(withSmp) "DBUS_EXCLUSIVE=yes DBUS_INVALIDATE=yes " else "")
override def applyOn(config: VexRiscvConfig): Unit = {
config.plugins += new DBusCachedPlugin(
@ -453,7 +455,9 @@ class DBusDimension extends VexRiscvDimension("DBus") {
catchUnaligned = catchAll,
withLrSc = withLrSc,
withAmo = withAmo,
earlyWaysHits = earlyWaysHits
earlyWaysHits = earlyWaysHits,
withExclusive = withSmp,
withInvalidate = withSmp
),
dBusCmdMasterPipe = dBusCmdMasterPipe,
dBusCmdSlavePipe = dBusCmdSlavePipe,