SpinalHDL 1.7.3
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commit
051d140c33
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@ -1,4 +1,4 @@
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val spinalVersion = "1.7.1"
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val spinalVersion = "1.7.3"
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lazy val root = (project in file(".")).
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settings(
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@ -75,5 +75,5 @@ class Stage() extends Area{
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dontSample.getOrElseUpdate(s, ArrayBuffer[Bool]()) += cond
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}
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def inputInit[T <: BaseType](stageable : Stageable[T],initValue : T) =
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Component.current.addPrePopTask(() => inputsDefault(stageable.asInstanceOf[Stageable[Data]]).asInstanceOf[T].getDrivingReg.init(initValue))
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Component.current.addPrePopTask(() => inputsDefault(stageable.asInstanceOf[Stageable[Data]]).asInstanceOf[T].getDrivingReg().init(initValue))
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}
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@ -120,6 +120,7 @@ object VexRiscvLitexSmpClusterCmdGen extends App {
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var netlistName = "VexRiscvLitexSmpCluster"
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var iTlbSize = 4
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var dTlbSize = 4
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var wishboneForce32b = false
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assert(new scopt.OptionParser[Unit]("VexRiscvLitexSmpClusterCmdGen") {
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help("help").text("prints this usage text")
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opt[Unit]("coherent-dma") action { (v, c) => coherentDma = true }
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@ -136,6 +137,7 @@ object VexRiscvLitexSmpClusterCmdGen extends App {
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opt[String]("aes-instruction") action { (v, c) => aesInstruction = v.toBoolean }
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opt[String]("out-of-order-decoder") action { (v, c) => outOfOrderDecoder = v.toBoolean }
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opt[String]("wishbone-memory" ) action { (v, c) => wishboneMemory = v.toBoolean }
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opt[String]("wishbone-force-32b" ) action { (v, c) => wishboneForce32b = v.toBoolean }
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opt[String]("fpu" ) action { (v, c) => fpu = v.toBoolean }
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opt[String]("cpu-per-fpu") action { (v, c) => cpuPerFpu = v.toInt }
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opt[String]("rvc") action { (v, c) => rvc = v.toBoolean }
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@ -173,7 +175,7 @@ object VexRiscvLitexSmpClusterCmdGen extends App {
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c
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}},
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withExclusiveAndInvalidation = coherency,
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forcePeripheralWidth = !wishboneMemory,
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forcePeripheralWidth = !wishboneMemory || wishboneForce32b,
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outOfOrderDecoder = outOfOrderDecoder,
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fpu = fpu,
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jtagHeaderIgnoreWidth = 0
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@ -530,7 +530,7 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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busy := True
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when(boot){
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when(input.i2f && !patched && input.value(31) && input.arg(0)){
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input.value.getDrivingReg(0, 32 bits) := B(input.value.asUInt.twoComplement(True).resize(32 bits))
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input.value.getDrivingReg()(0, 32 bits) := B(input.value.asUInt.twoComplement(True).resize(32 bits))
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patched := True
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} otherwise {
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shift.by := OHToUInt(OHMasking.first((ohInput).reversed))
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@ -1318,7 +1318,7 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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is(_15_XYY2){
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when(mulBuffer.valid) {
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state := Y_15_XYY2
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mulBuffer.payload.getDrivingReg := (U"11" << mulWidth-2) - (mulBuffer.payload)
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mulBuffer.payload.getDrivingReg() := (U"11" << mulWidth-2) - (mulBuffer.payload)
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}
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}
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is(Y_15_XYY2){
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@ -371,7 +371,7 @@ class DBusCachedPlugin(val config : DataCacheConfig,
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insert(MEMORY_VIRTUAL_ADDRESS) := cache.io.cpu.execute.address
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memory.input(MEMORY_VIRTUAL_ADDRESS)
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if(writeBack != null) addPrePopTask( () =>
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KeepAttribute(memory.input(MEMORY_VIRTUAL_ADDRESS).getDrivingReg)
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KeepAttribute(memory.input(MEMORY_VIRTUAL_ADDRESS).getDrivingReg())
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)
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}
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}
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@ -528,14 +528,14 @@ class DBusCachedPlugin(val config : DataCacheConfig,
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dBusAccess.rsp.error := cache.io.cpu.writeBack.unalignedAccess || cache.io.cpu.writeBack.accessError
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dBusAccess.rsp.redo := cache.io.cpu.redo
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component.addPrePopTask{() =>
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managementStage.input(IS_DBUS_SHARING).getDrivingReg clearWhen(dBusAccess.rsp.fire)
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managementStage.input(IS_DBUS_SHARING).getDrivingReg() clearWhen(dBusAccess.rsp.fire)
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when(forceDatapath){
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execute.output(REGFILE_WRITE_DATA) := dBusAccess.cmd.address.asBits
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}
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if(mmuAndBufferStage != execute) mmuAndBufferStage.input(IS_DBUS_SHARING) init(False)
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managementStage.input(IS_DBUS_SHARING) init(False)
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when(dBusAccess.rsp.valid){
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managementStage.input(IS_DBUS_SHARING).getDrivingReg := False
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managementStage.input(IS_DBUS_SHARING).getDrivingReg() := False
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}
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}
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}
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@ -390,7 +390,7 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
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//Check if the decode instruction is driven by a register
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val instructionDriver = try {
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decode.input(INSTRUCTION).getDrivingReg
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decode.input(INSTRUCTION).getDrivingReg()
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} catch {
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case _: Throwable => null
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}
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