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VexRiscv
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Fix inWfi naming, fix regressions

This commit is contained in:
Charles Papon 2019-12-20 00:21:55 +01:00
parent 0702f97806
commit 052c8dd602
2 changed files with 3 additions and 2 deletions
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3
src/main/scala/vexriscv/plugin/CsrPlugin.scala
View File

@ -388,6 +388,8 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
override def setup(pipeline: VexRiscv): Unit = {
import pipeline.config._
inWfi = False.addTag(Verilator.public)
thirdPartyWake = False
val defaultEnv = List[(Stageable[_ <: BaseType],Any)](
@ -911,7 +913,6 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
execute plug new Area{
import execute._
//Manage WFI instructions
inWfi = False.addTag(Verilator.public)
if(wfiOutput) out(inWfi)
val wfiWake = RegNext(interruptSpecs.map(_.cond).orR || thirdPartyWake) init(False)
if(wfiGenAsWait) when(arbitration.isValid && input(ENV_CTRL) === EnvCtrlEnum.WFI){

2
src/test/cpp/regression/main.cpp
View File

@ -1548,7 +1548,7 @@ public:
riscvRef.ipInput |= top->externalInterruptS << 9;
#endif
riscvRef.liveness(top->VexRiscv->execute_CsrPlugin_inWfi);
riscvRef.liveness(top->VexRiscv->CsrPlugin_inWfi);
if(top->VexRiscv->CsrPlugin_interruptJump){
if(riscvRefEnable) riscvRef.trap(true, top->VexRiscv->CsrPlugin_interrupt_code);
}