MulPlugin fix buffer interraction with partial regfile bypass

src/main/scala/vexriscv/plugin/HazardSimplePlugin.scala

@@ -31,6 +31,8 @@ class HazardSimplePlugin(bypassExecute : Boolean = false,
   override def build(pipeline: VexRiscv): Unit = {
     import pipeline._
     import pipeline.config._
+
+    pipeline plug new Area {
       val src0Hazard = False
       val src1Hazard = False
 
@@ -113,6 +115,7 @@ class HazardSimplePlugin(bypassExecute : Boolean = false,
       }
     }
   }
+}
 
 
 class NoHazardPlugin extends Plugin[VexRiscv] with HazardService {

src/main/scala/vexriscv/plugin/MulPlugin.scala

@@ -61,10 +61,9 @@ class MulPlugin(var inputBuffer : Boolean = false,
         when(arbitration.isValid && input(IS_MUL) && counter =/= delay){
           arbitration.haltItself := True
         }
-        when(!arbitration.isStuckByOthers){
+
         counter := counter + 1
-        }
+        when(!arbitration.isStuck || arbitration.isStuckByOthers){
-        when(!arbitration.isStuck){
           counter := 0
         }
       }