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VexRiscv
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CsrPlugin add wfiOutput

This commit is contained in:
Charles Papon 2019-12-19 22:55:17 +01:00
parent e25dfb4fbf
commit 0702f97806
1 changed files with 5 additions and 2 deletions
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7
src/main/scala/vexriscv/plugin/CsrPlugin.scala
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@ -69,7 +69,8 @@ case class CsrPluginConfig(
midelegAccess : CsrAccess = CsrAccess.NONE, midelegAccess : CsrAccess = CsrAccess.NONE,
pipelineCsrRead : Boolean = false, pipelineCsrRead : Boolean = false,
pipelinedInterrupt : Boolean = true, pipelinedInterrupt : Boolean = true,
deterministicInteruptionEntry : Boolean = false //Only used for simulatation purposes deterministicInteruptionEntry : Boolean = false, //Only used for simulatation purposes
wfiOutput : Boolean = false
){ ){
assert(!ucycleAccess.canWrite) assert(!ucycleAccess.canWrite)
def privilegeGen = userGen || supervisorGen def privilegeGen = userGen || supervisorGen
@ -343,6 +344,7 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
var selfException : Flow[ExceptionCause] = null var selfException : Flow[ExceptionCause] = null
var contextSwitching : Bool = null var contextSwitching : Bool = null
var thirdPartyWake : Bool = null var thirdPartyWake : Bool = null
var inWfi : Bool = null
override def askWake(): Unit = thirdPartyWake := True override def askWake(): Unit = thirdPartyWake := True
@ -909,7 +911,8 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
execute plug new Area{ execute plug new Area{
import execute._ import execute._
//Manage WFI instructions //Manage WFI instructions
val inWfi = False.addTag(Verilator.public) inWfi = False.addTag(Verilator.public)
if(wfiOutput) out(inWfi)
val wfiWake = RegNext(interruptSpecs.map(_.cond).orR || thirdPartyWake) init(False) val wfiWake = RegNext(interruptSpecs.map(_.cond).orR || thirdPartyWake) init(False)
if(wfiGenAsWait) when(arbitration.isValid && input(ENV_CTRL) === EnvCtrlEnum.WFI){ if(wfiGenAsWait) when(arbitration.isValid && input(ENV_CTRL) === EnvCtrlEnum.WFI){
inWfi := True inWfi := True