play around with CSR synthesis impact on design size

src/main/scala/vexriscv/demo/SynthesisBench.scala

@@ -6,8 +6,9 @@ import spinal.lib.eda.bench._
 import spinal.lib.eda.icestorm.IcestormStdTargets
 import spinal.lib.eda.xilinx.VivadoFlow
 import spinal.lib.io.InOutWrapper
-import vexriscv.VexRiscv
+import vexriscv.plugin.CsrAccess.{READ_ONLY, READ_WRITE, WRITE_ONLY}
-import vexriscv.plugin.DecoderSimplePlugin
+import vexriscv.{VexRiscv, VexRiscvConfig, plugin}
+import vexriscv.plugin.{BranchPlugin, CsrPlugin, CsrPluginConfig, DBusSimplePlugin, DecoderSimplePlugin, FullBarrelShifterPlugin, HazardSimplePlugin, IBusSimplePlugin, IntAluPlugin, LightShifterPlugin, NONE, RegFilePlugin, SrcPlugin, YamlPlugin}
 
 import scala.collection.mutable.ArrayBuffer
 import scala.util.Random
@@ -153,6 +154,7 @@ object VexRiscvSynthesisBench {
     }
 
 
+
 //    val rtls = List(twoStage, twoStageBarell, twoStageMulDiv, twoStageAll, smallestNoCsr, smallest, smallAndProductive, smallAndProductiveWithICache, fullNoMmuNoCache, noCacheNoMmuMaxPerf, fullNoMmuMaxPerf, fullNoMmu, full, linuxBalanced, linuxBalancedSmp)
     val rtls = List(linuxBalanced, linuxBalancedSmp)
 //    val rtls = List(smallest)
@@ -278,4 +280,100 @@ object AllSynthesisBench {
     MuraxSynthesisBench.main(args)
 
   }
+}
+
+
+
+object VexRiscvCustomSynthesisBench {
+  def main(args: Array[String]) {
+
+
+    def gen(csr : CsrPlugin) = new VexRiscv(
+      config = VexRiscvConfig(
+        plugins = List(
+          new IBusSimplePlugin(
+            resetVector = 0x80000000l,
+            cmdForkOnSecondStage = false,
+            cmdForkPersistence = false,
+            prediction = NONE,
+            catchAccessFault = false,
+            compressedGen = false
+          ),
+          new DBusSimplePlugin(
+            catchAddressMisaligned = false,
+            catchAccessFault = false
+          ),
+          new DecoderSimplePlugin(
+            catchIllegalInstruction = false
+          ),
+          new RegFilePlugin(
+            regFileReadyKind = plugin.SYNC,
+            zeroBoot = false
+          ),
+          new IntAluPlugin,
+          new SrcPlugin(
+            separatedAddSub = false,
+            executeInsertion = true
+          ),
+          csr,
+          new FullBarrelShifterPlugin(),
+          new HazardSimplePlugin(
+            bypassExecute           = true,
+            bypassMemory            = true,
+            bypassWriteBack         = true,
+            bypassWriteBackBuffer   = true,
+            pessimisticUseSrc       = false,
+            pessimisticWriteRegFile = false,
+            pessimisticAddressMatch = false
+          ),
+          new BranchPlugin(
+            earlyBranch = false,
+            catchAddressMisaligned = false
+          ),
+          new YamlPlugin("cpu0.yaml")
+        )
+      )
+    )
+
+
+    val fixedMtvec = new Rtl {
+      override def getName(): String = "Fixed MTVEC"
+      override def getRtlPath(): String = "fixedMtvec.v"
+      SpinalVerilog(gen(new CsrPlugin(CsrPluginConfig.smallest(0x80000000l))).setDefinitionName(getRtlPath().split("\\.").head))
+    }
+
+    val writeOnlyMtvec = new Rtl {
+      override def getName(): String = "write only MTVEC"
+      override def getRtlPath(): String = "woMtvec.v"
+      SpinalVerilog(gen(new CsrPlugin(CsrPluginConfig.smallest(null).copy(mtvecAccess = WRITE_ONLY))).setDefinitionName(getRtlPath().split("\\.").head))
+    }
+
+    val readWriteMtvec = new Rtl {
+      override def getName(): String = "read write MTVEC"
+      override def getRtlPath(): String = "wrMtvec.v"
+      SpinalVerilog(gen(new CsrPlugin(CsrPluginConfig.smallest(null).copy(mtvecAccess = READ_WRITE))).setDefinitionName(getRtlPath().split("\\.").head))
+    }
+
+    val fixedMtvecRoCounter = new Rtl {
+      override def getName(): String = "Fixed MTVEC, read only mcycle/minstret"
+      override def getRtlPath(): String = "fixedMtvecRoCounter.v"
+      SpinalVerilog(gen(new CsrPlugin(CsrPluginConfig.smallest(0x80000000l).copy(mcycleAccess = READ_ONLY, minstretAccess = READ_ONLY))).setDefinitionName(getRtlPath().split("\\.").head))
+    }
+
+
+    val rwMtvecRoCounter = new Rtl {
+      override def getName(): String = "read write MTVEC, read only mcycle/minstret"
+      override def getRtlPath(): String = "readWriteMtvecRoCounter.v"
+      SpinalVerilog(gen(new CsrPlugin(CsrPluginConfig.smallest(null).copy(mtvecAccess = READ_WRITE, mcycleAccess = READ_ONLY, minstretAccess = READ_ONLY))).setDefinitionName(getRtlPath().split("\\.").head))
+    }
+
+
+    //    val rtls = List(twoStage, twoStageBarell, twoStageMulDiv, twoStageAll, smallestNoCsr, smallest, smallAndProductive, smallAndProductiveWithICache, fullNoMmuNoCache, noCacheNoMmuMaxPerf, fullNoMmuMaxPerf, fullNoMmu, full, linuxBalanced, linuxBalancedSmp)
+    val rtls = List(fixedMtvec, writeOnlyMtvec, readWriteMtvec,fixedMtvecRoCounter, rwMtvecRoCounter)
+    //    val rtls = List(smallest)
+    val targets = XilinxStdTargets() ++ AlteraStdTargets() ++  IcestormStdTargets().take(1)
+
+    //    val targets = IcestormStdTargets()
+    Bench(rtls, targets)
+  }
 }

src/test/scala/vexriscv/TestIndividualFeatures.scala

@@ -577,8 +577,7 @@ object PlayFuture extends App{
 
 class MultithreadedFunSuite(threadCount : Int) extends FunSuite {
   val finalThreadCount = if(threadCount > 0) threadCount else {
-    val systemInfo = new oshi.SystemInfo
+    new oshi.SystemInfo().getHardware.getProcessor.getLogicalProcessorCount
-    systemInfo.getHardware.getProcessor.getLogicalProcessorCount
   }
   implicit val ec = ExecutionContext.fromExecutorService(
     new ForkJoinPool(finalThreadCount, ForkJoinPool.defaultForkJoinWorkerThreadFactory, null, true)