update smp config
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@ -68,13 +68,15 @@ object TestsWorkspace {
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catchIllegalAccess = true,
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catchAccessFault = true,
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asyncTagMemory = false,
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twoCycleRam = false,
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twoCycleRam = true,
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twoCycleCache = true
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// )
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),
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memoryTranslatorPortConfig = MmuPortConfig(
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portTlbSize = 4,
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latency = 0
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latency = 1,
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earlyRequireMmuLockup = true,
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earlyCacheHits = true
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)
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),
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// ).newTightlyCoupledPort(TightlyCoupledPortParameter("iBusTc", a => a(30 downto 28) === 0x0 && a(5))),
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@ -110,7 +112,9 @@ object TestsWorkspace {
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),
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memoryTranslatorPortConfig = MmuPortConfig(
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portTlbSize = 4,
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latency = 1
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latency = 1,
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earlyRequireMmuLockup = true,
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earlyCacheHits = true
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)
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),
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@ -9,7 +9,7 @@ import spinal.lib.bus.bmb.{Bmb, BmbArbiter, BmbDecoder, BmbExclusiveMonitor, Bmb
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import spinal.lib.com.jtag.Jtag
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import spinal.lib.com.jtag.sim.JtagTcp
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import vexriscv.ip.{DataCacheAck, DataCacheConfig, DataCacheMemBus, InstructionCache, InstructionCacheConfig}
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import vexriscv.plugin.{BranchPlugin, CsrPlugin, CsrPluginConfig, DBusCachedPlugin, DBusSimplePlugin, DebugPlugin, DecoderSimplePlugin, FullBarrelShifterPlugin, HazardSimplePlugin, IBusCachedPlugin, IBusSimplePlugin, IntAluPlugin, MmuPlugin, MmuPortConfig, MulDivIterativePlugin, MulPlugin, RegFilePlugin, STATIC, SrcPlugin, YamlPlugin}
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import vexriscv.plugin.{BranchPlugin, CsrPlugin, CsrPluginConfig, DBusCachedPlugin, DBusSimplePlugin, DYNAMIC_TARGET, DebugPlugin, DecoderSimplePlugin, FullBarrelShifterPlugin, HazardSimplePlugin, IBusCachedPlugin, IBusSimplePlugin, IntAluPlugin, MmuPlugin, MmuPortConfig, MulDivIterativePlugin, MulPlugin, RegFilePlugin, STATIC, SrcPlugin, YamlPlugin}
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import vexriscv.{Riscv, VexRiscv, VexRiscvConfig, plugin}
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import scala.collection.mutable
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@ -141,6 +141,8 @@ object VexRiscvSmpClusterGen {
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resetVector = resetVector,
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compressedGen = false,
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prediction = STATIC,
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historyRamSizeLog2 = 9,
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relaxPredictorAddress = true,
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injectorStage = false,
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relaxedPcCalculation = true,
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config = InstructionCacheConfig(
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@ -153,12 +155,15 @@ object VexRiscvSmpClusterGen {
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catchIllegalAccess = true,
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catchAccessFault = true,
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asyncTagMemory = false,
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twoCycleRam = true,
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twoCycleRam = false,
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twoCycleCache = true
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// )
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),
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memoryTranslatorPortConfig = MmuPortConfig(
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portTlbSize = 4
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portTlbSize = 4,
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latency = 1,
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earlyRequireMmuLockup = true,
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earlyCacheHits = true
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)
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),
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// ).newTightlyCoupledPort(TightlyCoupledPortParameter("iBusTc", a => a(30 downto 28) === 0x0 && a(5))),
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