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update smp config

This commit is contained in:
Dolu1990 2020-05-07 22:50:36 +02:00
parent 0e76cf9ac8
commit 0a159f06b2
2 changed files with 15 additions and 6 deletions
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10
src/main/scala/vexriscv/TestsWorkspace.scala
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@ -68,13 +68,15 @@ object TestsWorkspace {
catchIllegalAccess = true, catchIllegalAccess = true,
catchAccessFault = true, catchAccessFault = true,
asyncTagMemory = false, asyncTagMemory = false,
twoCycleRam = false, twoCycleRam = true,
twoCycleCache = true twoCycleCache = true
// ) // )
), ),
memoryTranslatorPortConfig = MmuPortConfig( memoryTranslatorPortConfig = MmuPortConfig(
portTlbSize = 4, portTlbSize = 4,
latency = 0 latency = 1,
earlyRequireMmuLockup = true,
earlyCacheHits = true
) )
), ),
// ).newTightlyCoupledPort(TightlyCoupledPortParameter("iBusTc", a => a(30 downto 28) === 0x0 && a(5))), // ).newTightlyCoupledPort(TightlyCoupledPortParameter("iBusTc", a => a(30 downto 28) === 0x0 && a(5))),
@ -110,7 +112,9 @@ object TestsWorkspace {
), ),
memoryTranslatorPortConfig = MmuPortConfig( memoryTranslatorPortConfig = MmuPortConfig(
portTlbSize = 4, portTlbSize = 4,
latency = 1 latency = 1,
earlyRequireMmuLockup = true,
earlyCacheHits = true
) )
), ),

11
src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
View File

@ -9,7 +9,7 @@ import spinal.lib.bus.bmb.{Bmb, BmbArbiter, BmbDecoder, BmbExclusiveMonitor, Bmb
import spinal.lib.com.jtag.Jtag import spinal.lib.com.jtag.Jtag
import spinal.lib.com.jtag.sim.JtagTcp import spinal.lib.com.jtag.sim.JtagTcp
import vexriscv.ip.{DataCacheAck, DataCacheConfig, DataCacheMemBus, InstructionCache, InstructionCacheConfig} import vexriscv.ip.{DataCacheAck, DataCacheConfig, DataCacheMemBus, InstructionCache, InstructionCacheConfig}
import vexriscv.plugin.{BranchPlugin, CsrPlugin, CsrPluginConfig, DBusCachedPlugin, DBusSimplePlugin, DebugPlugin, DecoderSimplePlugin, FullBarrelShifterPlugin, HazardSimplePlugin, IBusCachedPlugin, IBusSimplePlugin, IntAluPlugin, MmuPlugin, MmuPortConfig, MulDivIterativePlugin, MulPlugin, RegFilePlugin, STATIC, SrcPlugin, YamlPlugin} import vexriscv.plugin.{BranchPlugin, CsrPlugin, CsrPluginConfig, DBusCachedPlugin, DBusSimplePlugin, DYNAMIC_TARGET, DebugPlugin, DecoderSimplePlugin, FullBarrelShifterPlugin, HazardSimplePlugin, IBusCachedPlugin, IBusSimplePlugin, IntAluPlugin, MmuPlugin, MmuPortConfig, MulDivIterativePlugin, MulPlugin, RegFilePlugin, STATIC, SrcPlugin, YamlPlugin}
import vexriscv.{Riscv, VexRiscv, VexRiscvConfig, plugin} import vexriscv.{Riscv, VexRiscv, VexRiscvConfig, plugin}
import scala.collection.mutable import scala.collection.mutable
@ -141,6 +141,8 @@ object VexRiscvSmpClusterGen {
resetVector = resetVector, resetVector = resetVector,
compressedGen = false, compressedGen = false,
prediction = STATIC, prediction = STATIC,
historyRamSizeLog2 = 9,
relaxPredictorAddress = true,
injectorStage = false, injectorStage = false,
relaxedPcCalculation = true, relaxedPcCalculation = true,
config = InstructionCacheConfig( config = InstructionCacheConfig(
@ -153,12 +155,15 @@ object VexRiscvSmpClusterGen {
catchIllegalAccess = true, catchIllegalAccess = true,
catchAccessFault = true, catchAccessFault = true,
asyncTagMemory = false, asyncTagMemory = false,
twoCycleRam = true, twoCycleRam = false,
twoCycleCache = true twoCycleCache = true
// ) // )
), ),
memoryTranslatorPortConfig = MmuPortConfig( memoryTranslatorPortConfig = MmuPortConfig(
portTlbSize = 4 portTlbSize = 4,
latency = 1,
earlyRequireMmuLockup = true,
earlyCacheHits = true
) )
), ),
// ).newTightlyCoupledPort(TightlyCoupledPortParameter("iBusTc", a => a(30 downto 28) === 0x0 && a(5))), // ).newTightlyCoupledPort(TightlyCoupledPortParameter("iBusTc", a => a(30 downto 28) === 0x0 && a(5))),