Add many little options to reduce area
This commit is contained in:
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fb9ea11a5e
commit
0d92a5e5cd
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@ -47,6 +47,11 @@ trait ExceptionInhibitor{
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def inhibateException() : Unit
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}
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trait RegFileService{
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def readStage() : Stage
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}
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case class MemoryTranslatorCmd() extends Bundle{
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val isValid = Bool
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val virtualAddress = UInt(32 bits)
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@ -192,7 +192,7 @@ class BranchPlugin(earlyBranch : Boolean,
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//Apply branchs (JAL,JALR, Bxx)
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branchStage plug new Area {
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import branchStage._
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jumpInterface.valid := arbitration.isFiring && input(BRANCH_DO)
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jumpInterface.valid := arbitration.isValid && !arbitration.isStuckByOthers && input(BRANCH_DO)
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jumpInterface.payload := input(BRANCH_CALC)
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when(jumpInterface.valid) {
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@ -272,7 +272,7 @@ class BranchPlugin(earlyBranch : Boolean,
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val branchStage = if(earlyBranch) execute else memory
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branchStage plug new Area {
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import branchStage._
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jumpInterface.valid := input(BRANCH_DO) && arbitration.isFiring
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jumpInterface.valid := arbitration.isValid && !arbitration.isStuckByOthers && input(BRANCH_DO)
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jumpInterface.payload := input(BRANCH_CALC)
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when(jumpInterface.valid) {
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@ -349,7 +349,7 @@ class BranchPlugin(earlyBranch : Boolean,
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input(PC)
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}
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jumpInterface.valid := arbitration.isFiring && predictionMissmatch //Probably just isValid instead of isFiring is better
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jumpInterface.valid := arbitration.isValid && !arbitration.isStuckByOthers && predictionMissmatch //Probably just isValid instead of isFiring is better
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jumpInterface.payload := (input(BRANCH_DO) ? input(BRANCH_CALC) | input(NEXT_PC))
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@ -763,9 +763,13 @@ class CsrPlugin(config: CsrPluginConfig) extends Plugin[VexRiscv] with Exception
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val illegalAccess = arbitration.isValid && input(IS_CSR)
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val illegalInstruction = False
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if(selfException != null) {
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selfException.valid := illegalAccess || illegalInstruction
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selfException.code := 2
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selfException.valid := False
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selfException.code.assignDontCare()
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selfException.badAddr.assignDontCare()
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if(catchIllegalAccess) when(illegalAccess || illegalInstruction){
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selfException.valid := True
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selfException.code := 2
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}
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}
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//Manage MRET / SRET instructions
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@ -796,9 +800,9 @@ class CsrPlugin(config: CsrPluginConfig) extends Plugin[VexRiscv] with Exception
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val readData = B(0, 32 bits)
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val writeInstruction = arbitration.isValid && input(IS_CSR) && input(CSR_WRITE_OPCODE)
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val readInstruction = arbitration.isValid && input(IS_CSR) && input(CSR_READ_OPCODE)
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val writeEnable = writeInstruction && ! blockedBySideEffects // && readDataRegValid
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val readEnable = readInstruction && ! blockedBySideEffects // && !readDataRegValid
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val writeEnable = writeInstruction && ! blockedBySideEffects && !arbitration.isStuckByOthers// && readDataRegValid
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val readEnable = readInstruction && ! blockedBySideEffects && !arbitration.isStuckByOthers// && !readDataRegValid
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//arbitration.isStuckByOthers, in case of the hazardPlugin is in the executeStage
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// def readDataReg = memory.input(REGFILE_WRITE_DATA) //PIPE OPT
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@ -197,9 +197,12 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean = false,
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object ALIGNEMENT_FAULT extends Stageable(Bool)
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var memoryExceptionPort : Flow[ExceptionCause] = null
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var rspStage : Stage = null
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override def setup(pipeline: VexRiscv): Unit = {
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import Riscv._
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import pipeline.config._
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import pipeline._
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val decoderService = pipeline.service(classOf[DecoderService])
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@ -230,7 +233,7 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean = false,
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val rspStage = if(emitCmdInMemoryStage) pipeline.writeBack else pipeline.memory
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rspStage = if(stages.last == execute) execute else (if(emitCmdInMemoryStage) writeBack else memory)
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if(catchAccessFault || catchAddressMisaligned) {
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val exceptionService = pipeline.service(classOf[ExceptionService])
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memoryExceptionPort = exceptionService.newExceptionPort(rspStage)
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@ -243,11 +246,14 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean = false,
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dBus = master(DBusSimpleBus()).setName("dBus")
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//Emit dBus.cmd request
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val cmdStage = if(emitCmdInMemoryStage) memory else execute
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cmdStage plug new Area{
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import cmdStage._
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val cmdSent = if(rspStage == execute) RegInit(False) setWhen(dBus.cmd.fire) clearWhen(!execute.arbitration.isStuck) else False
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insert(ALIGNEMENT_FAULT) := {
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if (catchAddressMisaligned)
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(dBus.cmd.size === 2 && dBus.cmd.address(1 downto 0) =/= 0) || (dBus.cmd.size === 1 && dBus.cmd.address(0 downto 0) =/= 0)
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@ -255,7 +261,7 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean = false,
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False
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}
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dBus.cmd.valid := arbitration.isValid && input(MEMORY_ENABLE) && !arbitration.isStuckByOthers && !arbitration.isFlushed && !input(ALIGNEMENT_FAULT)
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dBus.cmd.valid := arbitration.isValid && input(MEMORY_ENABLE) && !arbitration.isStuckByOthers && !arbitration.isFlushed && !input(ALIGNEMENT_FAULT) && !cmdSent
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dBus.cmd.wr := input(INSTRUCTION)(5)
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dBus.cmd.address := input(SRC_ADD).asUInt
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dBus.cmd.size := input(INSTRUCTION)(13 downto 12).asUInt
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@ -264,7 +270,7 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean = false,
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U(1) -> input(RS2)(15 downto 0) ## input(RS2)(15 downto 0),
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default -> input(RS2)(31 downto 0)
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)
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when(arbitration.isValid && input(MEMORY_ENABLE) && !dBus.cmd.ready && !input(ALIGNEMENT_FAULT)){
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when(arbitration.isValid && input(MEMORY_ENABLE) && !dBus.cmd.ready && !input(ALIGNEMENT_FAULT) && !cmdSent){
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arbitration.haltItself := True
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}
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@ -283,9 +289,8 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean = false,
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}
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//Collect dBus.rsp read responses
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val rspStage = if(emitCmdInMemoryStage) writeBack else memory
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rspStage plug new Area {
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import rspStage._
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val s = rspStage; import s._
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insert(MEMORY_READ_DATA) := dBus.rsp.data
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@ -313,7 +318,7 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean = false,
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}
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assert(!(dBus.rsp.ready && input(MEMORY_ENABLE) && arbitration.isValid && arbitration.isStuck),"DBusSimplePlugin doesn't allow memory stage stall when read happend")
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if(rspStage != execute) assert(!(dBus.rsp.ready && input(MEMORY_ENABLE) && arbitration.isValid && arbitration.isStuck),"DBusSimplePlugin doesn't allow memory stage stall when read happend")
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}
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//Reformat read responses, REGFILE_WRITE_DATA overriding
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@ -19,6 +19,6 @@ class HazardPessimisticPlugin() extends Plugin[VexRiscv] {
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import pipeline.config._
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val writesInPipeline = stages.dropWhile(_ != execute).map(s => s.arbitration.isValid && s.input(REGFILE_WRITE_VALID)) :+ RegNext(stages.last.arbitration.isValid && stages.last.input(REGFILE_WRITE_VALID))
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decode.arbitration.haltItself.setWhen(decode.arbitration.isValid && writesInPipeline.orR)
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decode.arbitration.haltByOther.setWhen(decode.arbitration.isValid && writesInPipeline.orR)
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}
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}
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@ -26,18 +26,20 @@ class HazardSimplePlugin(bypassExecute : Boolean = false,
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val src0Hazard = False
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val src1Hazard = False
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val readStage = service(classOf[RegFileService]).readStage()
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def trackHazardWithStage(stage : Stage,bypassable : Boolean, runtimeBypassable : Stageable[Bool]): Unit ={
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val runtimeBypassableValue = if(runtimeBypassable != null) stage.input(runtimeBypassable) else True
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val addr0Match = if(pessimisticAddressMatch) True else stage.input(INSTRUCTION)(rdRange) === decode.input(INSTRUCTION)(rs1Range)
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val addr1Match = if(pessimisticAddressMatch) True else stage.input(INSTRUCTION)(rdRange) === decode.input(INSTRUCTION)(rs2Range)
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val addr0Match = if(pessimisticAddressMatch) True else stage.input(INSTRUCTION)(rdRange) === readStage.input(INSTRUCTION)(rs1Range)
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val addr1Match = if(pessimisticAddressMatch) True else stage.input(INSTRUCTION)(rdRange) === readStage.input(INSTRUCTION)(rs2Range)
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when(stage.arbitration.isValid && stage.input(REGFILE_WRITE_VALID)) {
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if (bypassable) {
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when(runtimeBypassableValue) {
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when(addr0Match) {
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decode.input(RS1) := stage.output(REGFILE_WRITE_DATA)
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readStage.input(RS1) := stage.output(REGFILE_WRITE_DATA)
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}
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when(addr1Match) {
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decode.input(RS2) := stage.output(REGFILE_WRITE_DATA)
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readStage.input(RS2) := stage.output(REGFILE_WRITE_DATA)
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}
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}
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}
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@ -64,15 +66,15 @@ class HazardSimplePlugin(bypassExecute : Boolean = false,
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writeBackWrites.data := stages.last.output(REGFILE_WRITE_DATA)
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val writeBackBuffer = writeBackWrites.stage()
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val addr0Match = if(pessimisticAddressMatch) True else writeBackBuffer.address === decode.input(INSTRUCTION)(rs1Range)
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val addr1Match = if(pessimisticAddressMatch) True else writeBackBuffer.address === decode.input(INSTRUCTION)(rs2Range)
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val addr0Match = if(pessimisticAddressMatch) True else writeBackBuffer.address === readStage.input(INSTRUCTION)(rs1Range)
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val addr1Match = if(pessimisticAddressMatch) True else writeBackBuffer.address === readStage.input(INSTRUCTION)(rs2Range)
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when(writeBackBuffer.valid) {
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if (bypassWriteBackBuffer) {
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when(addr0Match) {
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decode.input(RS1) := writeBackBuffer.data
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readStage.input(RS1) := writeBackBuffer.data
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}
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when(addr1Match) {
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decode.input(RS2) := writeBackBuffer.data
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readStage.input(RS2) := writeBackBuffer.data
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}
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} else {
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when(addr0Match) {
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@ -86,20 +88,20 @@ class HazardSimplePlugin(bypassExecute : Boolean = false,
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if(withWriteBackStage) trackHazardWithStage(writeBack,bypassWriteBack,null)
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if(withMemoryStage) trackHazardWithStage(memory ,bypassMemory ,BYPASSABLE_MEMORY_STAGE)
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trackHazardWithStage(execute ,bypassExecute , if(stages.last == execute) null else BYPASSABLE_EXECUTE_STAGE)
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if(readStage != execute) trackHazardWithStage(execute ,bypassExecute , if(stages.last == execute) null else BYPASSABLE_EXECUTE_STAGE)
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if(!pessimisticUseSrc) {
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when(!decode.input(RS1_USE)) {
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when(!readStage.input(RS1_USE)) {
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src0Hazard := False
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}
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when(!decode.input(RS2_USE)) {
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when(!readStage.input(RS2_USE)) {
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src1Hazard := False
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}
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}
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when(decode.arbitration.isValid && (src0Hazard || src1Hazard)){
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decode.arbitration.haltItself := True
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when(readStage.arbitration.isValid && (src0Hazard || src1Hazard)){
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readStage.arbitration.haltByOther := True
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}
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}
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}
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@ -153,7 +153,8 @@ class IBusSimplePlugin(resetVector : BigInt,
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busLatencyMin : Int = 1,
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pendingMax : Int = 7,
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injectorStage : Boolean = true,
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rspHoldValue : Boolean = false
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rspHoldValue : Boolean = false,
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singleInstructionPipeline : Boolean = false
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) extends IBusFetcherImpl(
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resetVector = resetVector,
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keepPcPlus4 = keepPcPlus4,
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@ -168,7 +169,7 @@ class IBusSimplePlugin(resetVector : BigInt,
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var iBus : IBusSimpleBus = null
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var decodeExceptionPort : Flow[ExceptionCause] = null
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if(rspHoldValue) assert(busLatencyMin == 1)
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if(rspHoldValue) assert(busLatencyMin <= 1)
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override def setup(pipeline: VexRiscv): Unit = {
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super.setup(pipeline)
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@ -197,6 +198,11 @@ class IBusSimplePlugin(resetVector : BigInt,
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//This implementation keep the cmd on the bus until it's executed or the the pipeline is flushed
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def stage = iBusRsp.stages(if(cmdForkOnSecondStage) 1 else 0)
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stage.halt setWhen(stage.input.valid && (!cmd.valid || !cmd.ready))
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if(singleInstructionPipeline) {
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cmd.valid := stage.input.valid && pendingCmd =/= pendingMax && !stages.map(_.arbitration.isValid).orR
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assert(injectorStage == false)
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assert(iBusRsp.stages.dropWhile(_ != stage).length <= 2)
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}else
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cmd.valid := stage.input.valid && stage.output.ready && pendingCmd =/= pendingMax
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cmd.pc := stage.input.payload(31 downto 2) @@ "00"
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} else new Area{
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@ -230,7 +236,10 @@ class IBusSimplePlugin(resetVector : BigInt,
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c.io.flush := flush
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rspBufferOutput << c.io.pop
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} else new Area{
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rspBufferOutput << iBus.rsp.throwWhen(discardCounter =/= 0).toStream
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val rspStream = iBus.rsp.throwWhen(discardCounter =/= 0).toStream
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val validReg = RegInit(False) setWhen(rspStream.valid) clearWhen(rspBufferOutput.ready)
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rspBufferOutput << rspStream
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rspBufferOutput.valid setWhen(validReg)
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}
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val fetchRsp = FetchRsp()
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@ -0,0 +1,23 @@
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package vexriscv.plugin
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import spinal.core._
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import spinal.lib._
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import vexriscv._
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class NoPipeliningPlugin() extends Plugin[VexRiscv] {
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override def setup(pipeline: VexRiscv): Unit = {
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import pipeline.config._
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val decoderService = pipeline.service(classOf[DecoderService])
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decoderService.addDefault(HAS_SIDE_EFFECT, False)
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}
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override def build(pipeline: VexRiscv): Unit = {
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import pipeline._
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import pipeline.config._
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val writesInPipeline = stages.dropWhile(_ != execute).map(s => s.arbitration.isValid && s.input(REGFILE_WRITE_VALID)) :+ RegNext(stages.last.arbitration.isValid && stages.last.input(REGFILE_WRITE_VALID))
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decode.arbitration.haltByOther.setWhen(stagesFromExecute.map(_.arbitration.isValid).orR)
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}
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}
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@ -13,13 +13,17 @@ object SYNC extends RegFileReadKind
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class RegFilePlugin(regFileReadyKind : RegFileReadKind,
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zeroBoot : Boolean = false,
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x0Init : Boolean = true,
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writeRfInMemoryStage : Boolean = false,
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readInExecute : Boolean = false) extends Plugin[VexRiscv]{
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readInExecute : Boolean = false,
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syncUpdateOnStall : Boolean = true) extends Plugin[VexRiscv] with RegFileService{
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import Riscv._
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// assert(!writeRfInMemoryStage)
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override def readStage(): Stage = if(readInExecute) pipeline.execute else pipeline.decode
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override def setup(pipeline: VexRiscv): Unit = {
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import pipeline.config._
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val decoderService = pipeline.service(classOf[DecoderService])
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@ -51,7 +55,7 @@ class RegFilePlugin(regFileReadyKind : RegFileReadKind,
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val srcInstruction = regFileReadyKind match{
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case `ASYNC` => input(INSTRUCTION)
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case `SYNC` if !readInExecute => input(INSTRUCTION_ANTICIPATED)
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case `SYNC` if readInExecute => Mux(execute.arbitration.isStuck, execute.input(INSTRUCTION), decode.input(INSTRUCTION))
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case `SYNC` if readInExecute => if(syncUpdateOnStall) Mux(execute.arbitration.isStuck, execute.input(INSTRUCTION), decode.input(INSTRUCTION)) else decode.input(INSTRUCTION)
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}
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val regFileReadAddress1 = srcInstruction(Riscv.rs1Range).asUInt
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@ -59,7 +63,9 @@ class RegFilePlugin(regFileReadyKind : RegFileReadKind,
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val (rs1Data,rs2Data) = regFileReadyKind match{
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case `ASYNC` => (global.regFile.readAsync(regFileReadAddress1),global.regFile.readAsync(regFileReadAddress2))
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case `SYNC` => (global.regFile.readSync(regFileReadAddress1),global.regFile.readSync(regFileReadAddress2))
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case `SYNC` =>
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val enable = if(!syncUpdateOnStall) !readStage.arbitration.isStuck else null
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(global.regFile.readSync(regFileReadAddress1, enable),global.regFile.readSync(regFileReadAddress2, enable))
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}
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insert(RS1) := rs1Data
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@ -77,10 +83,19 @@ class RegFilePlugin(regFileReadyKind : RegFileReadKind,
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regFileWrite.data := output(REGFILE_WRITE_DATA)
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//CPU will initialise constant register zero in the first cycle
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regFileWrite.valid setWhen(RegNext(False) init(True))
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if(x0Init) {
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val boot = RegNext(False) init (True)
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regFileWrite.valid setWhen (boot)
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if (writeStage != execute) {
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inputInit[Bits](REGFILE_WRITE_DATA, 0)
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inputInit[Bits](INSTRUCTION, 0)
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} else {
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when(boot) {
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regFileWrite.address := 0
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regFileWrite.data := 0
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}
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}
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}
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}
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}
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}
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@ -152,7 +152,8 @@ class LightShifterPlugin extends Plugin[VexRiscv]{
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val isShift = input(SHIFT_CTRL) =/= ShiftCtrlEnum.DISABLE
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val amplitudeReg = Reg(UInt(5 bits))
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val amplitude = isActive ? amplitudeReg | input(SRC2)(4 downto 0).asUInt
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val shiftInput = isActive ? memory.input(REGFILE_WRITE_DATA) | input(SRC1)
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val shiftReg = ifGen(!withMemoryStage) (RegNextWhen(execute.output(REGFILE_WRITE_DATA), !arbitration.isStuckByOthers))
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val shiftInput = isActive ? (if(withMemoryStage) memory.input(REGFILE_WRITE_DATA) else shiftReg) | input(SRC1)
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val done = amplitude(4 downto 1) === 0
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@ -10,7 +10,7 @@ cd VexRiscv
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sudo git init
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sudo git add *
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sudo git commit -m miaou
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export VEXRISCV_REGRESSION_CONFIG_COUNT=16
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export VEXRISCV_REGRESSION_CONFIG_COUNT=64
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export VEXRISCV_REGRESSION_FREERTOS_COUNT=yes
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sbt test
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cd ..
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