Merge remote-tracking branch 'origin/master' into dev
# Conflicts: # build.sbt
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commit
0df4ec45ad
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@ -39,7 +39,7 @@ This repository hosts a RISC-V implementation written in SpinalHDL. Here are som
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- Optional interrupts and exception handling with Machine, [Supervisor] and [User] modes as defined in the [RISC-V Privileged ISA Specification v1.10](https://riscv.org/specifications/privileged-isa/).
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- Two implementations of shift instructions: Single cycle and shiftNumber cycles
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- Each stage can have optional bypass or interlock hazard logic
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- Linux compatible
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- Linux compatible (SoC : https://github.com/enjoy-digital/linux-on-litex-vexriscv)
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- Zephyr compatible
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- [FreeRTOS port](https://github.com/Dolu1990/FreeRTOS-RISCV)
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@ -879,9 +879,10 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
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import execute._
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//Manage WFI instructions
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val inWfi = False.addTag(Verilator.public)
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val wfiWake = RegNext(interruptSpecs.map(_.cond).orR) init(False)
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if(wfiGenAsWait) when(arbitration.isValid && input(ENV_CTRL) === EnvCtrlEnum.WFI){
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inWfi := True
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when(!interrupt){
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when(!wfiWake){
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arbitration.haltItself := True
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}
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}
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@ -23,6 +23,7 @@ class DBusCachedPlugin(val config : DataCacheConfig,
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dBusCmdMasterPipe : Boolean = false,
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dBusCmdSlavePipe : Boolean = false,
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dBusRspSlavePipe : Boolean = false,
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relaxedMemoryTranslationRegister : Boolean = false,
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csrInfo : Boolean = false) extends Plugin[VexRiscv] with DBusAccessService {
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import config._
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@ -49,6 +50,7 @@ class DBusCachedPlugin(val config : DataCacheConfig,
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object MEMORY_LRSC extends Stageable(Bool)
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object MEMORY_AMO extends Stageable(Bool)
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object IS_DBUS_SHARING extends Stageable(Bool())
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object MEMORY_VIRTUAL_ADDRESS extends Stageable(UInt(32 bits))
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override def setup(pipeline: VexRiscv): Unit = {
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import Riscv._
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@ -220,6 +222,8 @@ class DBusCachedPlugin(val config : DataCacheConfig,
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when(cache.io.cpu.redo && arbitration.isValid && input(MEMORY_ENABLE)){
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arbitration.haltItself := True
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}
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if(relaxedMemoryTranslationRegister) insert(MEMORY_VIRTUAL_ADDRESS) := cache.io.cpu.execute.address
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}
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memory plug new Area{
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@ -227,7 +231,7 @@ class DBusCachedPlugin(val config : DataCacheConfig,
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cache.io.cpu.memory.isValid := arbitration.isValid && input(MEMORY_ENABLE)
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cache.io.cpu.memory.isStuck := arbitration.isStuck
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cache.io.cpu.memory.isRemoved := arbitration.removeIt
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cache.io.cpu.memory.address := U(input(REGFILE_WRITE_DATA))
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cache.io.cpu.memory.address := (if(relaxedMemoryTranslationRegister) input(MEMORY_VIRTUAL_ADDRESS) else U(input(REGFILE_WRITE_DATA)))
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cache.io.cpu.memory.mmuBus <> mmuBus
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cache.io.cpu.memory.mmuBus.rsp.isIoAccess setWhen(pipeline(DEBUG_BYPASS_CACHE) && !cache.io.cpu.memory.isWrite)
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@ -3,7 +3,11 @@ package vexriscv.plugin
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import spinal.core._
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import vexriscv.VexRiscv
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class ExternalInterruptArrayPlugin(arrayWidth : Int = 32, maskCsrId : Int = 0xBC0, pendingsCsrId : Int = 0xFC0) extends Plugin[VexRiscv]{
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class ExternalInterruptArrayPlugin(arrayWidth : Int = 32,
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machineMaskCsrId : Int = 0xBC0,
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machinePendingsCsrId : Int = 0xFC0,
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supervisorMaskCsrId : Int = 0x9C0,
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supervisorPendingsCsrId : Int = 0xDC0) extends Plugin[VexRiscv]{
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var externalInterruptArray : Bits = null
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override def setup(pipeline: VexRiscv): Unit = {
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@ -12,10 +16,15 @@ class ExternalInterruptArrayPlugin(arrayWidth : Int = 32, maskCsrId : Int = 0xBC
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override def build(pipeline: VexRiscv): Unit = {
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val csr = pipeline.service(classOf[CsrPlugin])
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val mask = Reg(Bits(arrayWidth bits)) init(0)
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val pendings = mask & RegNext(externalInterruptArray)
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csr.externalInterrupt.setAsDirectionLess() := pendings.orR
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csr.rw(maskCsrId, mask)
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csr.r(pendingsCsrId, pendings)
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val externalInterruptArrayBuffer = RegNext(externalInterruptArray)
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def gen(maskCsrId : Int, pendingsCsrId : Int, interruptPin : Bool) = new Area {
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val mask = Reg(Bits(arrayWidth bits)) init(0)
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val pendings = mask & externalInterruptArrayBuffer
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interruptPin.setAsDirectionLess() := pendings.orR
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csr.rw(maskCsrId, mask)
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csr.r(pendingsCsrId, pendings)
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}
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gen(machineMaskCsrId, machinePendingsCsrId, csr.externalInterrupt)
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if(csr.config.supervisorGen) gen(supervisorMaskCsrId, supervisorPendingsCsrId, csr.externalInterruptS)
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}
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}
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@ -396,11 +396,14 @@ class DBusDimension extends VexRiscvDimension("DBus") {
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var wayCount = 0
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val withLrSc = catchAll
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val withAmo = catchAll && r.nextBoolean()
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val dBusRspSlavePipe, relaxedMemoryTranslationRegister, earlyWaysHits = r.nextBoolean()
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val dBusCmdMasterPipe, dBusCmdSlavePipe = false //As it create test bench issues
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do{
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cacheSize = 512 << r.nextInt(5)
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wayCount = 1 << r.nextInt(3)
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}while(cacheSize/wayCount < 512 || (catchAll && cacheSize/wayCount > 4096))
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new VexRiscvPosition("Cached" + "S" + cacheSize + "W" + wayCount + "BPL" + bytePerLine) {
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new VexRiscvPosition("Cached" + "S" + cacheSize + "W" + wayCount + "BPL" + bytePerLine + (if(dBusCmdMasterPipe) "Cmp " else "") + (if(dBusCmdSlavePipe) "Csp " else "") + (if(dBusRspSlavePipe) "Rsp " else "") + (if(relaxedMemoryTranslationRegister) "Rmtr " else "") + (if(earlyWaysHits) "Ewh " else "")) {
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override def testParam = "DBUS=CACHED " + (if(withLrSc) "LRSC=yes " else "") + (if(withAmo) "AMO=yes " else "")
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override def applyOn(config: VexRiscvConfig): Unit = {
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@ -416,8 +419,13 @@ class DBusDimension extends VexRiscvDimension("DBus") {
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catchIllegal = catchAll,
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catchUnaligned = catchAll,
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withLrSc = withLrSc,
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withAmo = withAmo
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withAmo = withAmo,
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earlyWaysHits = earlyWaysHits
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),
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dBusCmdMasterPipe = dBusCmdMasterPipe,
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dBusCmdSlavePipe = dBusCmdSlavePipe,
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dBusRspSlavePipe = dBusRspSlavePipe,
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relaxedMemoryTranslationRegister = relaxedMemoryTranslationRegister,
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memoryTranslatorPortConfig = mmuConfig
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)
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}
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