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VexRiscv
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This commit is contained in:
Dolu1990 2022-10-26 10:25:50 +02:00
parent 63dd787bce
commit 0e531515ac
1 changed files with 0 additions and 4 deletions
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4
src/main/scala/vexriscv/demo/VexRiscvAxi4LinuxPlicClint.scala
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@ -132,7 +132,6 @@ object VexRiscvAxi4LinuxPlicClint{
}
case plugin: DBusCachedPlugin => {
plugin.dBus.setAsDirectionLess()
Axi4SpecRenamer(
master(plugin.dBus.toAxi4Shared().toAxi4().toFullConfig())
.setName("dBusAxi")
@ -148,9 +147,6 @@ object VexRiscvAxi4LinuxPlicClint{
.addTag(ResetEmitterTag(plugin.debugClockDomain))
.parent = null //Avoid the io bundle to be interpreted as a QSys conduit
}
case _ =>
}
for (plugin <- cpuConfig.plugins) plugin match {
case plugin: CsrPlugin => {
plugin.timerInterrupt setAsDirectionLess() := cpu.clintCtrl.io.timerInterrupt(0)
plugin.softwareInterrupt setAsDirectionLess() := cpu.clintCtrl.io.softwareInterrupt(0)