Add some coremark results
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README.md
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README.md
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@ -83,33 +83,33 @@ VexRiscv small and productive (RV32I, 0.82 DMIPS/Mhz) ->
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Cyclone IV -> 137 Mhz 1,103 LUT 522 FF
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iCE40 -> 65 Mhz 1593 LC
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VexRiscv small and productive with I$ (RV32I, 0.72 DMIPS/Mhz, 4KB-I$) ->
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VexRiscv small and productive with I$ (RV32I, 0.70 DMIPS/Mhz, 4KB-I$) ->
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Artix 7 -> 314 Mhz 721 LUT 562 FF
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Cyclone V -> 152 Mhz 504 ALMs
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Cyclone IV -> 142 Mhz 1,146 LUT 528 FF
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iCE40 -> 69 Mhz 1661 LC
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VexRiscv full no cache (RV32IM, 1.22 DMIPS/Mhz, single cycle barrel shifter, debug module, catch exceptions, static branch) ->
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VexRiscv full no cache (RV32IM, 1.21 DMIPS/Mhz 2.30 Coremark/Mhz, single cycle barrel shifter, debug module, catch exceptions, static branch) ->
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Artix 7 -> 325 Mhz 1448 LUT 976 FF
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Cyclone V -> 141 Mhz 957 ALMs
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Cyclone IV -> 139 Mhz 2,001 LUT 966 FF
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VexRiscv full (RV32IM, 1.21 DMIPS/Mhz with cache trashing, 4KB-I$,4KB-D$, single cycle barrel shifter, debug module, catch exceptions, static branch) ->
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VexRiscv full (RV32IM, 1.21 DMIPS/Mhz 2.30 Coremark/Mhz with cache trashing, 4KB-I$,4KB-D$, single cycle barrel shifter, debug module, catch exceptions, static branch) ->
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Artix 7 -> 241 Mhz 1692 LUT 1202 FF
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Cyclone V -> 132 Mhz 1,127 ALMs
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Cyclone IV -> 124 Mhz 2,296 LUT 1,115 FF
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VexRiscv full max dmips/mhz -> (RV32IM, 1.44 DMIPS/Mhz, 16KB-I$,16KB-D$, single cycle barrel shifter, debug module, catch exceptions, dynamic branch prediction in the fetch stage, branch and shift operations done in the Execute stage) ->
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VexRiscv full max dmips/mhz -> (RV32IM, 1.44 DMIPS/Mhz 2.70 Coremark/Mhz,, 16KB-I$,16KB-D$, single cycle barrel shifter, debug module, catch exceptions, dynamic branch prediction in the fetch stage, branch and shift operations done in the Execute stage) ->
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Artix 7 -> 195 Mhz 1824 LUT 1110 FF
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Cyclone V -> 83 Mhz 1,067 ALMs
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Cyclone IV -> 78 Mhz 2,335 LUT 1,045 FF
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VexRiscv full with MMU (RV32IM, 1.26 DMIPS/Mhz with cache trashing, 4KB-I$, 4KB-D$, single cycle barrel shifter, debug module, catch exceptions, dynamic branch, MMU) ->
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VexRiscv full with MMU (RV32IM, 1.24 DMIPS/Mhz 2.35 Coremark/Mhz, with cache trashing, 4KB-I$, 4KB-D$, single cycle barrel shifter, debug module, catch exceptions, dynamic branch, MMU) ->
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Artix 7 -> 218 Mhz 1966 LUT 1551 FF
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Cyclone V -> 123 Mhz 1,298 ALMs
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Cyclone IV -> 109 Mhz 2,703 LUT 1,498 FF
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VexRiscv linux balanced (RV32IMA, 1.21 DMIPS/Mhz with cache trashing, 4KB-I$, 4KB-D$, single cycle barrel shifter, catch exceptions, static branch, MMU, Supervisor, Compatible with mainstream linux) ->
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VexRiscv linux balanced (RV32IMA, 1.21 DMIPS/Mhz 2.27 Coremark/Mhz, with cache trashing, 4KB-I$, 4KB-D$, single cycle barrel shifter, catch exceptions, static branch, MMU, Supervisor, Compatible with mainstream linux) ->
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Artix 7 -> 239 Mhz 2483 LUT 2134 FF
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Cyclone V -> 130 Mhz 1,636 ALMs
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Cyclone IV -> 116 Mhz 3,324 LUT 2,010 FF
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