TestIndividual is now fully random
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Dolu1990
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69
README.md
69
README.md
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@ -332,17 +332,19 @@ You can find multiples software examples and demo there : https://github.com/Spi
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There is some measurements of Murax SoC timings and area :
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```
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Murax interlocked stages (0.45 DMIPS/Mhz) ->
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Artix 7 -> 305 Mhz 1004 LUT 1297 FF
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Cyclone V -> 160 Mhz 744 ALMs
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Cyclone IV -> 148 Mhz 1,522 LUT 1,255 FF
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ICE40-HX -> 51 Mhz 2402 LC (icestorm)
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Murax interlocked stages (0.45 DMIPS/Mhz, 8 bits GPIO) ->
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Artix 7 -> 299 Mhz 984 LUT 1186 FF
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Cyclone V -> 175 Mhz 710 ALMs
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Cyclone IV -> 137 Mhz 1,436 LUT 1,193 FF
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iCE40 -> 48 Mhz 2337 LC (icestorm)
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iCE40Ultra -> 20 Mhz 2337 LC (icestorm)
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MuraxFast bypassed stages (0.65 DMIPS/Mhz) ->
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Artix 7 -> 312 Mhz 1240 LUT 1330 FF
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Cyclone V -> 159 Mhz 884 ALMs
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Cyclone IV -> 142 Mhz 1,755 LUT 1,289 FF
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ICE40-HX -> 50 Mhz, 2787 LC (icestorm)
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MuraxFast bypassed stages (0.65 DMIPS/Mhz, 8 bits GPIO) ->
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Artix 7 -> 294 Mhz 1128 LUT 1219 FF
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Cyclone V -> 165 Mhz 840 ALMs
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Cyclone IV -> 141 Mhz 1,680 LUT 1,227 FF
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iCE40 -> 48 Mhz 2702 LC (icestorm)
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iCE40Ultra -> 22 Mhz 2702 LC (icestorm)
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```
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There is some scripts to generate the SoC and call the icestorm toolchain there : scripts/Murax/
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@ -414,14 +416,10 @@ val cpu = new VexRiscv(
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config = VexRiscvConfig(
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//Provide a list of plugins which will futher add their logic into the CPU
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plugins = List(
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new PcManagerSimplePlugin(
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new IBusSimplePlugin(
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resetVector = 0x00000000l,
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relaxedPcCalculation = true
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),
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new IBusSimplePlugin(
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interfaceKeepData = false,
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catchAccessFault = false
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),
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new DBusSimplePlugin(
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catchAddressMisaligned = false,
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catchAccessFault = false
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@ -447,8 +445,7 @@ val cpu = new VexRiscv(
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),
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new BranchPlugin(
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earlyBranch = false,
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catchAddressMisaligned = false,
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prediction = NONE
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catchAddressMisaligned = false
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),
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new YamlPlugin("cpu0.yaml")
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)
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@ -616,7 +613,6 @@ So again, if you generate the CPU without any plugin, it will only contain the 5
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This chapter is describing plugins currently implemented.
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- [PcManagerSimplePlugin](#pcmanagersimpleplugin)
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- [IBusSimplePlugin](#ibussimpleplugin)
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- [IBusCachedPlugin](#ibuscachedplugin)
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- [DecoderSimplePlugin](#decodersimpleplugin)
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@ -649,24 +645,24 @@ This plugin implement the programme counter and over an jump service to all plug
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| relaxedPcCalculation | Boolean | By default jump have an asynchronous immediate effect on the program counter, which allow to reduce the branch penalties by one cycle but could reduce the FMax as it will combinatorialy drive the instruction bus address signal. To avoid this you can set this parameter to true, which will make the jump affecting the programm counter in a sequancial way, which will cut the combinatorial path but add one additional cycle of penalty when a jump occur. |
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The jump interface implemented by this plugin allow all other plugin to request jumps. The stage argument specify from which stage the jump is asked, which will allow the PcManagerSimplePlugin plugin to manage priorities between jump requests.
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```scala
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trait JumpService{
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def createJumpInterface(stage : Stage) : Flow[UInt]
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}
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```
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This plugin operate into the prefetch stage.
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#### IBusSimplePlugin
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This plugin fetch instruction via a very simple and neutral memory interface going outside the CPU.
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This plugin implement the CPU frontend (instruction fetch) via a very simple and neutral memory interface going outside the CPU.
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| Parameters | type | description |
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| ------ | ----------- | ------ |
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| interfaceKeepData | Boolean | Specify if the read response interface keep the data until the next one, or if it's only present a single cycle.|
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| catchAccessFault | Boolean | If an the read response specify an read error and this parameter is true, it will generate an CPU exception trap |
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| resetVector | BigInt | Address of the program counter after the reset |
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| relaxedPcCalculation | Boolean | By default jump have an asynchronous immediate effect on the program counter, which allow to reduce the branch penalties by one cycle but could reduce the FMax as it will combinatorialy drive the instruction bus address signal. To avoid this you can set this parameter to true, which will make the jump affecting the programm counter in a sequancial way, which will cut the combinatorial path but add one additional cycle of penalty when a jump occur. |
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| relaxedBusCmdValid | Boolean | Same than relaxedPcCalculation, but for the iBus.cmd.valid pin. |
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| compressedGen | Boolean | Enable RVC support |
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| busLatencyMin | Int | Specify the minimal latency between the iBus.cmd and iBus.rsp, which will add the corresponding number of stages into the frontend to keep the IPC to 1.|
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| injectorStage | Boolean | Add a stage between the frontend and the decode stage of the CPU to improve FMax. (busLatencyMin + injectorStage) should be at least two. |
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| prediction | BranchPrediction | Can be set to NONE/STATIC/DYNAMIC/DYNAMIC_TARGET to specify the branch predictor implementation, see bellow for more descriptions |
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| historyRamSizeLog2 | Int | Specify the number of entries in the direct mapped prediction cache of DYNAMIC/DYNAMIC_TARGET implementation. 2 pow historyRamSizeLog2 entries |
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There is the SimpleBus interface definition
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@ -700,7 +696,14 @@ There is at least one cycle latency between que cmd and the rsp. the rsp.ready f
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Note that bridges are implemented to convert this interface into AXI4 and Avalon
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This plugin fit in the fetch stage
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The jump interface implemented by this plugin allow all other plugin to request jumps. The stage argument specify from which stage the jump is asked, which will allow the PcManagerSimplePlugin plugin to manage priorities between jump requests.
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```scala
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trait JumpService{
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def createJumpInterface(stage : Stage) : Flow[UInt]
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}
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```
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#### IBusCachedPlugin
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@ -719,6 +722,11 @@ Simple and light multi way instruction cache.
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| catchIllegalAccess | Boolean | Catch when an memory access is done on non valid memory address (MMU) |
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| catchAccessFault | Boolean | Catch when the memeory bus is responding with an error |
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| catchMemoryTranslationMiss | Boolean | Catch when the MMU miss a TLB |
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| resetVector | BigInt | Address of the program counter after the reset |
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| relaxedPcCalculation | Boolean | By default jump have an asynchronous immediate effect on the program counter, which allow to reduce the branch penalties by one cycle but could reduce the FMax as it will combinatorialy drive the instruction bus address signal. To avoid this you can set this parameter to true, which will make the jump affecting the programm counter in a sequancial way, which will cut the combinatorial path but add one additional cycle of penalty when a jump occur. |
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| compressedGen | Boolean | Enable RVC support |
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| prediction | BranchPrediction | Can be set to NONE/STATIC/DYNAMIC/DYNAMIC_TARGET to specify the branch predictor implementation, see bellow for more descriptions |
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| historyRamSizeLog2 | Int | Specify the number of entries in the direct mapped prediction cache of DYNAMIC/DYNAMIC_TARGET implementation. 2 pow historyRamSizeLog2 entries |
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Note : If you enable the twoCycleRam and and the wayCount is bigger than one, then the register file plugin should be configured to read the regFile in a asyncronus manner.
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@ -813,18 +821,15 @@ Implement SLL/SRL/SRA instructions by using an full barriel shifter, so it execu
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#### BranchPlugin
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This plugin implement all branch/jump instructions (JAL/JALR/BEQ/BNE/BLT/BGE/BLTU/BGEU) with some optional branch prediction. Each of those branch prediction could have been implemented into separated plugins.
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This plugin implement all branch/jump instructions (JAL/JALR/BEQ/BNE/BLT/BGE/BLTU/BGEU) with primitives used by the cpu frontend plugins to implement branch prediction. The prediction implementation is set in the frontend plugins (IBusX)
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| Parameters | type | description |
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| ------ | ----------- | ------ |
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| earlyBranch | Boolean | By default the branch is done in the Memory stage to relax timings, but if this option is set it's done in the Execute stage|
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| catchAddressMisaligned | Boolean | If a jump/branch is done in an unaligned PC address, it will fire an trap exception |
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| prediction | BranchPrediction | Can be set to NONE/STATIC/DYNAMIC/DYNAMIC_TARGET to specify the branch predictor implementation, see bellow for more descriptions |
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| historyRamSizeLog2 | Int | Specify the number of entries in the direct mapped prediction cache of DYNAMIC/DYNAMIC_TARGET implementation. 2 pow historyRamSizeLog2 entries |
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Each miss predicted jumps will produce between 2 and 4 cycles penalty depending the `earlyBranch` and the `PcManagerSimplePlugin.relaxedPcCalculation` configurations
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##### Prediction NONE
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No prediction, each PC changes due to a jump/branch will produce a penalty.
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@ -31,38 +31,39 @@ object TestsWorkspace {
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SpinalConfig(mergeAsyncProcess = false).generateVerilog {
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val configFull = VexRiscvConfig(
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plugins = List(
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new IBusSimplePlugin(
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resetVector = 0x80000000l,
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relaxedPcCalculation = true,
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relaxedBusCmdValid = false,
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prediction = DYNAMIC_TARGET,
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historyRamSizeLog2 = 10,
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catchAccessFault = true,
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compressedGen = false,
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busLatencyMin = 1
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),
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// new IBusCachedPlugin(
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// new IBusSimplePlugin(
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// resetVector = 0x80000000l,
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// compressedGen = true,
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// relaxedPcCalculation = true,
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// relaxedBusCmdValid = false,
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// prediction = DYNAMIC_TARGET,
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// config = InstructionCacheConfig(
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// cacheSize = 1024*16,
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// bytePerLine = 32,
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// wayCount = 1,
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// addressWidth = 32,
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// cpuDataWidth = 32,
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// memDataWidth = 32,
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// catchIllegalAccess = false,
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// catchAccessFault = true,
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// catchMemoryTranslationMiss = false,
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// asyncTagMemory = false,
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// twoCycleRam = false,
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// twoCycleCache = true
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// ),
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// memoryTranslatorPortConfig = MemoryTranslatorPortConfig(
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// portTlbSize = 4
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// )
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// historyRamSizeLog2 = 10,
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// catchAccessFault = true,
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// compressedGen = false,
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// busLatencyMin = 1
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// ),
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new IBusCachedPlugin(
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resetVector = 0x80000000l,
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compressedGen = true,
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prediction = DYNAMIC_TARGET,
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injectorStage = true,
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config = InstructionCacheConfig(
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cacheSize = 1024*16,
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bytePerLine = 32,
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wayCount = 1,
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addressWidth = 32,
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cpuDataWidth = 32,
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memDataWidth = 32,
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catchIllegalAccess = true,
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catchAccessFault = true,
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catchMemoryTranslationMiss = true,
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asyncTagMemory = false,
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twoCycleRam = false,
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twoCycleCache = true
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),
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memoryTranslatorPortConfig = MemoryTranslatorPortConfig(
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portTlbSize = 4
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)
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),
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// new DBusSimplePlugin(
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// catchAddressMisaligned = true,
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// catchAccessFault = true,
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@ -1,6 +1,6 @@
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package vexriscv.plugin
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import vexriscv._
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import vexriscv.{plugin, _}
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import vexriscv.ip._
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import spinal.core._
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import spinal.lib._
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@ -16,7 +16,8 @@ class IBusCachedPlugin(resetVector : BigInt = 0x80000000l,
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compressedGen : Boolean = false,
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keepPcPlus4 : Boolean = false,
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config : InstructionCacheConfig,
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memoryTranslatorPortConfig : Any = null) extends IBusFetcherImpl(
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memoryTranslatorPortConfig : Any = null,
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injectorStage : Boolean = false) extends IBusFetcherImpl(
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catchAccessFault = config.catchAccessFault,
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resetVector = resetVector,
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keepPcPlus4 = keepPcPlus4,
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@ -27,7 +28,7 @@ class IBusCachedPlugin(resetVector : BigInt = 0x80000000l,
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relaxedPcCalculation = relaxedPcCalculation,
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prediction = prediction,
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historyRamSizeLog2 = historyRamSizeLog2,
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injectorStage = !config.twoCycleCache){
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injectorStage = !config.twoCycleCache || injectorStage){
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import config._
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var iBus : InstructionCacheMemBus = null
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@ -133,7 +134,7 @@ class IBusCachedPlugin(resetVector : BigInt = 0x80000000l,
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cache.io.cpu.decode.pc := iBusRsp.inputPipeline(1).payload
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cache.io.cpu.decode.isUser := (if (privilegeService != null) privilegeService.isUser(decode) else False)
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if((!twoCycleRam || wayCount == 1) && !compressedGen){
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if((!twoCycleRam || wayCount == 1) && !compressedGen && !injectorStage){
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decode.insert(INSTRUCTION_ANTICIPATED) := Mux(decode.arbitration.isStuck, decode.input(INSTRUCTION), cache.io.cpu.fetch.data)
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}
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}
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@ -1 +1 @@
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.word 0x7912a23
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.word 0x3c12083
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@ -8,6 +8,7 @@ import vexriscv.demo._
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import vexriscv.ip.{DataCacheConfig, InstructionCacheConfig}
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import vexriscv.plugin._
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import scala.collection.mutable
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import scala.collection.mutable.ArrayBuffer
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import scala.sys.process._
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import scala.util.Random
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@ -20,6 +21,16 @@ abstract class ConfigDimension[T](val name: String) {
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abstract class VexRiscvDimension(name: String) extends ConfigDimension[VexRiscvPosition](name)
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abstract class ConfigPosition[T](val name: String) {
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def applyOn(config: T): Unit
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var dimension : ConfigDimension[_] = null
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def isCompatibleWith(positions : Seq[ConfigPosition[T]]) : Boolean = true
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}
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abstract class VexRiscvPosition(name: String) extends ConfigPosition[VexRiscvConfig](name){
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def testParam : String = ""
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}
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class ShiftDimension extends VexRiscvDimension("Shift") {
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override val positions = List(
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new VexRiscvPosition("FullLate") {
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@ -256,14 +267,16 @@ class IBusDimension extends VexRiscvDimension("IBus") {
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wayCount <- List(1, 4);
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cacheSize <- List(512, 4096);
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compressed <- List(false, true);
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injectorStage <- List(false, true);
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relaxedPcCalculation <- List(false, true);
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if !(!twoCycleCache && twoCycleRam ) && !(prediction != NONE && (wayCount == 1 || cacheSize == 4096 ))) yield new VexRiscvPosition("Cached" + (if(twoCycleCache) "2cc" else "") + (if(twoCycleRam) "2cr" else "") + "S" + cacheSize + "W" + wayCount + (if(relaxedPcCalculation) "Relax" else "") + (if(compressed) "Rvc" else "") + prediction.getClass.getTypeName().replace("$","")) with InstructionAnticipatedPosition{
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if !(!twoCycleCache && twoCycleRam ) && !(prediction != NONE && (wayCount == 1 || cacheSize == 4096 ))) yield new VexRiscvPosition("Cached" + (if(twoCycleCache) "2cc" else "") + (if(injectorStage) "Injstage" else "") + (if(twoCycleRam) "2cr" else "") + "S" + cacheSize + "W" + wayCount + (if(relaxedPcCalculation) "Relax" else "") + (if(compressed) "Rvc" else "") + prediction.getClass.getTypeName().replace("$","")) with InstructionAnticipatedPosition{
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override def testParam = "IBUS=CACHED" + (if(compressed) " COMPRESSED=yes" else "")
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override def applyOn(config: VexRiscvConfig): Unit = config.plugins += new IBusCachedPlugin(
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resetVector = 0x80000000l,
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compressedGen = compressed,
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prediction = prediction,
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relaxedPcCalculation = relaxedPcCalculation,
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injectorStage = injectorStage,
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config = InstructionCacheConfig(
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cacheSize = cacheSize,
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bytePerLine = 32,
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@ -335,15 +348,24 @@ class DBusDimension extends VexRiscvDimension("DBus") {
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abstract class ConfigPosition[T](val name: String) {
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def applyOn(config: T): Unit
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var dimension : ConfigDimension[_] = null
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def isCompatibleWith(positions : Seq[ConfigPosition[T]]) : Boolean = true
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trait CatchAllPosition
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class CsrDimension extends VexRiscvDimension("Src") {
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override val positions = List(
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new VexRiscvPosition("None") {
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override def applyOn(config: VexRiscvConfig): Unit = {}
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override def testParam = "CSR=no"
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},
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new VexRiscvPosition("All") with CatchAllPosition{
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override def applyOn(config: VexRiscvConfig): Unit = config.plugins += new CsrPlugin(CsrPluginConfig.all)
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override def testParam = "CSR=no"
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}
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)
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}
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abstract class VexRiscvPosition(name: String) extends ConfigPosition[VexRiscvConfig](name){
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def testParam : String = ""
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}
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class TestIndividualFeatures extends FunSuite {
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def doCmd(cmd: String): String = {
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@ -366,14 +388,15 @@ class TestIndividualFeatures extends FunSuite {
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val dimensions = List(
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new IBusDimension,
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new DBusDimension,
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new MulDivDimension,
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new ShiftDimension,
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new BranchDimension,
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new HazardDimension,
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new RegFileDimension,
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new SrcDimension,
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new IBusDimension,
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new DBusDimension
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new CsrDimension
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)
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@ -382,8 +405,11 @@ class TestIndividualFeatures extends FunSuite {
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case Nil => List(stack)
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}
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val usedPositions = mutable.HashSet[VexRiscvPosition]();
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val positionsCount = dimensions.map(d => d.positions.length).sum
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def doTest(positionsToApply : List[VexRiscvPosition], prefix : String = ""): Unit ={
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usedPositions ++= positionsToApply
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def gen = {
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SpinalVerilog{
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val config = VexRiscvConfig(
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@ -404,7 +430,7 @@ class TestIndividualFeatures extends FunSuite {
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gen
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}
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test(prefix + name + "_test") {
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val testCmd = "make clean run REDO=10 CSR=no MMU=no DEBUG_PLUGIN=no " + (positionsToApply).map(_.testParam).mkString(" ")
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val testCmd = "make clean run REDO=5 MMU=no DEBUG_PLUGIN=no " + (positionsToApply).map(_.testParam).mkString(" ")
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val str = doCmd(testCmd)
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assert(!str.contains("FAIL"))
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val intFind = "(\\d+\\.?)+".r
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@ -414,7 +440,8 @@ class TestIndividualFeatures extends FunSuite {
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dimensions.foreach(d => d.positions.foreach(_.dimension = d))
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for(i <- 0 until 40){
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for(i <- 0 until 200){
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var positions : List[VexRiscvPosition] = null
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do{
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positions = dimensions.map(d => d.positions(Random.nextInt(d.positions.size)))
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@ -422,14 +449,13 @@ class TestIndividualFeatures extends FunSuite {
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doTest(positions," random_" + i + "_")
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}
|
||||
|
||||
for (dimension <- dimensions) {
|
||||
for (position <- dimension.positions/* if position.name.contains("Cached")*/) {
|
||||
for(defaults <- genDefaultsPositions(dimensions.filter(_ != dimension))){
|
||||
doTest(position :: defaults)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
println(s"${usedPositions.size}/$positionsCount positions")
|
||||
|
||||
// for (dimension <- dimensions) {
|
||||
// for (position <- dimension.positions/* if position.name.contains("Cached")*/) {
|
||||
// for(defaults <- genDefaultsPositions(dimensions.filter(_ != dimension))){
|
||||
// doTest(position :: defaults)
|
||||
// }
|
||||
// }
|
||||
// }
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue