Add YAML feature to store CPU info

build.sbt

@@ -8,5 +8,6 @@ EclipseKeys.withSource := true
 
 libraryDependencies ++= Seq(
   "com.github.spinalhdl" % "spinalhdl-core_2.11" % "0.10.13",
-  "com.github.spinalhdl" % "spinalhdl-lib_2.11" % "0.10.13"
+  "com.github.spinalhdl" % "spinalhdl-lib_2.11" % "0.10.13",
+  "org.yaml" % "snakeyaml" % "1.8"
 )

cpu0.yaml

@@ -0,0 +1,4 @@
+iBus: !!SpinalRiscv.BusReport
+  flushInstructions: [16399]
+  info: !!SpinalRiscv.CacheReport {bytePerLine: 32, size: 4096}
+  kind: cached

src/main/scala/SpinalRiscv/Plugin/DBusCachedPlugin.scala

@@ -62,6 +62,26 @@ class DBusCachedPlugin(config : DataCacheConfig, memoryTranslatorPortConfig : An
 
     if(pipeline.serviceExist(classOf[PrivilegeService]))
       privilegeService = pipeline.service(classOf[PrivilegeService])
+
+    if(pipeline.serviceExist(classOf[ReportService])){
+      val report = pipeline.service(classOf[ReportService])
+      report.add("dBus" -> {
+        val e = new BusReport()
+        val c = new CacheReport()
+        e.kind = "cached"
+        e.flushInstructions.add(0x13 | (1 << 7)) ////ADDI x1, x0, 0
+        for(idx <- 0 until cacheSize by bytePerLine){
+          e.flushInstructions.add(0x13 + (1 << 7)  + (1 << 15) + (bytePerLine << 20)) //ADDI x1, x1, 32
+          e.flushInstructions.add(0x7000500F + (1 << 15)) //Clean invalid data cache way x1
+        }
+
+        e.info = c
+        c.size = cacheSize
+        c.bytePerLine = bytePerLine
+
+        e
+      })
+    }
   }
 
   override def build(pipeline: VexRiscv): Unit = {

src/main/scala/SpinalRiscv/Plugin/IBusCachedPlugin.scala

@@ -39,6 +39,22 @@ class IBusCachedPlugin(config : InstructionCacheConfig, askMemoryTranslation : B
 
     if(pipeline.serviceExist(classOf[PrivilegeService]))
       privilegeService = pipeline.service(classOf[PrivilegeService])
+
+    if(pipeline.serviceExist(classOf[ReportService])){
+      val report = pipeline.service(classOf[ReportService])
+      report.add("iBus" -> {
+        val e = new BusReport()
+        val c = new CacheReport()
+        e.kind = "cached"
+        e.flushInstructions.add(0x400F) //invalid instruction cache
+
+        e.info = c
+        c.size = cacheSize
+        c.bytePerLine = bytePerLine
+
+        e
+      })
+    }
   }
 
   override def build(pipeline: VexRiscv): Unit = {

src/main/scala/SpinalRiscv/Plugin/YamlPlugin.scala

@@ -0,0 +1,32 @@
+package SpinalRiscv.Plugin
+
+import java.util
+
+import SpinalRiscv.{ReportService, VexRiscv}
+import org.yaml.snakeyaml.{DumperOptions, Yaml}
+
+
+/**
+ * Created by spinalvm on 09.06.17.
+ */
+class YamlPlugin(path : String) extends Plugin[VexRiscv] with ReportService{
+
+  val content = new util.HashMap[String, Object]()
+
+  def add(that : (String,Object)) : Unit  = content.put(that._1,that._2)
+
+  override def setup(pipeline: VexRiscv): Unit = {
+
+  }
+
+  override def build(pipeline: VexRiscv): Unit = {
+    val options = new DumperOptions()
+    options.setWidth(50)
+    options.setIndent(4)
+    options.setCanonical(true)
+    options.setDefaultFlowStyle(DumperOptions.FlowStyle.BLOCK)
+
+    val yaml = new Yaml()
+    yaml.dump(content, new java.io.FileWriter(path))
+  }
+}

src/main/scala/SpinalRiscv/Services.scala

@@ -1,8 +1,12 @@
 package SpinalRiscv
 
+import java.util
+
 import spinal.core._
 import spinal.lib._
 
+import scala.beans.BeanProperty
+
 trait JumpService{
   def createJumpInterface(stage : Stage) : Flow[UInt]
 }
@@ -56,3 +60,18 @@ case class MemoryTranslatorBus() extends Bundle with IMasterSlave{
 trait MemoryTranslator{
   def newTranslationPort(stage : Stage, args : Any) : MemoryTranslatorBus
 }
+
+
+trait ReportService{
+  def add(that : (String,Object)) : Unit
+}
+
+class BusReport{
+  @BeanProperty var kind = ""
+  @BeanProperty var flushInstructions = new util.LinkedList[Int]()
+  @BeanProperty var info : Object = null
+}
+class CacheReport {
+  @BeanProperty var size = 0
+  @BeanProperty var bytePerLine = 0
+}

src/main/scala/SpinalRiscv/demo/Briey.scala

@@ -200,7 +200,8 @@ class Briey(config: BrieyConfig) extends Component{
             earlyBranch = false,
             catchAddressMisaligned = false,
             prediction = NONE
-          )
+          ),
+          new YamlPlugin("cpu0.yaml")
         )
       )
 

src/test/cpp/briey/installs.txt

@@ -1,3 +1,6 @@
+sudo apt-get install libYAML-dev
+
+
 sudo apt-get update
 sudo apt-get install build-essential software-properties-common -y
 sudo add-apt-repository ppa:ubuntu-toolchain-r/test -y
@@ -16,4 +19,4 @@ sudo ./b2 install
 
 
 echo "using gcc : 6.3 : /usr/bin/g++-6 ; " >> tools/build/src/user-config.jam
-bjam --toolset=gcc-6
+bjam --toolset=gcc-6

src/test/cpp/briey/jtag.gtkw

@@ -1,22 +1,22 @@
 [*]
 [*] GTKWave Analyzer v3.3.58 (w)1999-2014 BSI
-[*] Thu Jun  8 18:59:55 2017
+[*] Fri Jun  9 08:05:42 2017
 [*]
 [dumpfile] "/home/spinalvm/Spinal/VexRiscv/src/test/cpp/briey/Briey.vcd"
-[dumpfile_mtime] "Thu Jun  8 18:59:41 2017"
-[dumpfile_size] 1075034305
+[dumpfile_mtime] "Fri Jun  9 08:05:37 2017"
+[dumpfile_size] 2070466159
 [savefile] "/home/spinalvm/Spinal/VexRiscv/src/test/cpp/briey/jtag.gtkw"
-[timestart] 152443780000
+[timestart] 51980000000
 [size] 1776 953
 [pos] -1 -353
-*-19.000000 152586930000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+*-33.000000 62611680000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] TOP.
 [treeopen] TOP.Briey.
 [treeopen] TOP.Briey.axi_jtagCtrl.
 [sst_width] 288
 [signals_width] 302
 [sst_expanded] 1
-[sst_vpaned_height] 279
+[sst_vpaned_height] 503
 @28
 TOP.io_jtag_tck
 TOP.io_jtag_tdi
@@ -24,15 +24,17 @@ TOP.io_jtag_tdo
 TOP.io_jtag_tms
 @22
 TOP.Briey.axi_jtagCtrl.jtagBridge_1.jtag_tap_fsm_state[3:0]
-@23
 TOP.Briey.axi_core_cpu.debug_bus_cmd_payload_address[7:0]
-@22
 TOP.Briey.axi_core_cpu.debug_bus_cmd_payload_data[31:0]
-@28
+@29
 TOP.Briey.axi_core_cpu.debug_bus_cmd_payload_wr
+@28
 TOP.Briey.axi_core_cpu.debug_bus_cmd_ready
 TOP.Briey.axi_core_cpu.debug_bus_cmd_valid
 @22
 TOP.Briey.axi_core_cpu.debug_bus_rsp_data[31:0]
+@28
+TOP.Briey.axi_core_cpu.DebugPlugin_haltIt
+TOP.Briey.axi_core_cpu.DebugPlugin_haltedByBreak
 [pattern_trace] 1
 [pattern_trace] 0