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VexRiscv
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Merge remote-tracking branch 'origin/expand-satp' into expose-satp

This commit is contained in:
buncram 2022-12-20 19:31:15 +08:00
parent b86047901a bf3521f86a
commit 11f391eadf
1 changed files with 5 additions and 3 deletions
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8
src/main/scala/vexriscv/plugin/MmuPlugin.scala
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@ -97,13 +97,14 @@ class MmuPlugin(ioRange : UInt => Bool,
new Area {
val mode = out(RegInit(False))
val asid = out(Reg(Bits(9 bits)))
val ppn = out(Reg(UInt(20 bits)))
// Bottom 20 bits are used in implementation, but top 2 bits are still stored for OS use.
val ppn = out(Reg(UInt(22 bits)))
}
} else {
new Area {
val mode = RegInit(False)
val asid = Reg(Bits(9 bits))
val ppn = Reg(UInt(20 bits))
val ppn = Reg(UInt(22 bits))
}
}
@ -243,7 +244,8 @@ class MmuPlugin(ioRange : UInt => Bool,
}
is(State.L1_CMD){
dBusAccess.cmd.valid := True
dBusAccess.cmd.address := csr.satp.ppn @@ vpn(1) @@ U"00"
// RV spec allows for 34-bit phys address in Sv32 mode; we only implement 32 bits and ignore the top 2 bits of satp.
dBusAccess.cmd.address := csr.satp.ppn(19 downto 0) @@ vpn(1) @@ U"00"
when(dBusAccess.cmd.ready){
state := State.L1_RSP
}