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VexRiscv
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Update readme perf

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Charles Papon 2019-06-16 18:07:04 +02:00
parent 635ef51f82
commit 12c3ab16ae
1 changed files with 2 additions and 2 deletions
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@ -100,9 +100,9 @@ VexRiscv full (RV32IM, 1.21 DMIPS/Mhz 2.30 Coremark/Mhz with cache trashing, 4KB
Cyclone IV -> 133 Mhz 2,298 LUT 1,096 FF Cyclone IV -> 133 Mhz 2,298 LUT 1,096 FF
VexRiscv full max dmips/mhz -> (RV32IM, 1.44 DMIPS/Mhz 2.70 Coremark/Mhz,, 16KB-I$,16KB-D$, single cycle barrel shifter, debug module, catch exceptions, dynamic branch prediction in the fetch stage, branch and shift operations done in the Execute stage) -> VexRiscv full max dmips/mhz -> (RV32IM, 1.44 DMIPS/Mhz 2.70 Coremark/Mhz,, 16KB-I$,16KB-D$, single cycle barrel shifter, debug module, catch exceptions, dynamic branch prediction in the fetch stage, branch and shift operations done in the Execute stage) ->
Artix 7 -> 195 Mhz 1943 LUT 1111 FF Artix 7 -> 193 Mhz 1758 LUT 1094 FF
Cyclone V -> 90 Mhz 1,089 ALMs Cyclone V -> 90 Mhz 1,089 ALMs
Cyclone IV -> 80 Mhz 2,335 LUT 1,048 FF Cyclone IV -> 79 Mhz 2,336 LUT 1,048 FF
VexRiscv full with MMU (RV32IM, 1.24 DMIPS/Mhz 2.35 Coremark/Mhz, with cache trashing, 4KB-I$, 4KB-D$, single cycle barrel shifter, debug module, catch exceptions, dynamic branch, MMU) -> VexRiscv full with MMU (RV32IM, 1.24 DMIPS/Mhz 2.35 Coremark/Mhz, with cache trashing, 4KB-I$, 4KB-D$, single cycle barrel shifter, debug module, catch exceptions, dynamic branch, MMU) ->
Artix 7 -> 239 Mhz 2029 LUT 1585 FF Artix 7 -> 239 Mhz 2029 LUT 1585 FF