boot
This commit is contained in:
Dolu1990
commit
130ed6345c
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@ -0,0 +1,37 @@
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*.class
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*.log
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*.bak
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# sbt specific
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.cache/
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.history/
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.lib/
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dist/*
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target
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lib_managed/
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src_managed/
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project/boot/
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project/plugins/project/
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# Scala-IDE specific
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.scala_dependencies
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.worksheet
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.idea
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out
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# Eclipse
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bin/
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.classpath
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.project
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.settings
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.cache-main
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#User
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/*.vhd
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/*.v
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*.cf
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*.json
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*.vcd
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!tester/src/test/resources/*.vhd
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class PcManagerSimple(resetVector : BigInt,pcWidth : Int,fastFetchCmdPcCalculation : Boolean) extends Plugin[SpinalRiscv] with PcManagerService{
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import StandardStageables._
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//FetchService interface
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case class JumpInfo(pc: UInt, cond: Bool, stage: Stage)
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val jumpInfos = ArrayBuffer[JumpInfo]()
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override def jumpTo(pc: UInt, cond: Bool, stage: Stage): Unit = jumpInfos += JumpInfo(pc,cond,stage)
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override def build(pipeline: SpinalRiscv): Unit = {
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import pipeline.prefetch
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prefetch.plug(new Area {
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import prefetch._
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//PC calculation without Jump
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val pcReg = Reg(UInt(pcWidth bit)) init(resetVector)
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val inc = RegInit(False)
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val pc = if(fastFetchCmdPcCalculation){
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val pcPlus4 = pcReg + 4
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pcPlus4.addAttribute("keep")
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Mux(inc,pcPlus4,pcReg)
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}else{
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pcReg + (inc ? U(4) | U(0))
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}
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//Stage always valid
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arbitration.isValid := True
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//FetchService hardware implementation
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val jumpInfoSorted = jumpInfos.sortWith((a,b) => pipeline.indexOf(a.stage) > pipeline.indexOf(b.stage))
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val jumpRequestValids = jumpInfoSorted.map(_.cond)
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val jumpRequestPcs = jumpInfoSorted.map(_.pc)
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val pcLoad = Flow(pcReg)
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pcLoad.valid := jumpInfos.foldLeft(False)(_ || _.cond)
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pcLoad.payload := MuxOH(jumpRequestValids,jumpRequestPcs)
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//Register managments
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when(pcLoad.valid){
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pc := pcLoad.payload
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inc := False
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pcReg := pc
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}
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when(arbitration.isFiring){
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inc := True
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pcReg := pc
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}
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//Pipeline insertions
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insert(PC) := pc
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})
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}
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}
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name := "SpinalBaseProject"
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version := "1.0"
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scalaVersion := "2.11.6"
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EclipseKeys.withSource := true
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libraryDependencies ++= Seq(
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"com.github.spinalhdl" % "spinalhdl-core_2.11" % "latest.release",
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"com.github.spinalhdl" % "spinalhdl-lib_2.11" % "latest.release"
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)
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addSbtPlugin("com.typesafe.sbteclipse" % "sbteclipse-plugin" % "4.0.0")
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package SpinalRiscv
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import spinal.core._
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import scala.collection.mutable
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import scala.collection.mutable.ArrayBuffer
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trait Pipeline {
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type T <: Pipeline
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val plugins = ArrayBuffer[Plugin[T]]()
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var stages = ArrayBuffer[Stage]()
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val services = ArrayBuffer[Any]()
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def indexOf(stage : Stage) = stages.indexOf(stage)
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def service[T](clazz : Class[T]) = {
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val filtered = services.filter(_.getClass == clazz)
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assert(filtered.length == 1)
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filtered.head.asInstanceOf[T]
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}
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def build(): Unit ={
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//Build plugins
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plugins.foreach(_.build(this.asInstanceOf[T]))
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//Interconnect stages
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class KeyInfo{
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var insertStageId = Int.MaxValue
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var lastInputStageId = Int.MinValue
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var lastOutputStageId = Int.MinValue
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def addInputStageIndex(stageId : Int): Unit = {
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require(stageId > insertStageId)
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lastInputStageId = Math.max(lastInputStageId,stageId)
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lastOutputStageId = Math.max(lastOutputStageId,stageId-1)
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}
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def addOutputStageIndex(stageId : Int): Unit = {
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require(stageId >= insertStageId)
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if(stageId != insertStageId) lastInputStageId = Math.min(lastInputStageId,stageId)
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lastOutputStageId = Math.max(lastOutputStageId,stageId)
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}
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def setInsertStageId(stageId : Int) = insertStageId = stageId
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}
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val inputOutputKeys = mutable.HashMap[Stageable[Data],KeyInfo]()
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for(stageIndex <- 0 until stages.length; stage = stages(stageIndex)){
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stage.inserts.keysIterator.foreach(signal => inputOutputKeys.getOrElseUpdate(signal,new KeyInfo).setInsertStageId(stageIndex))
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}
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for(stageIndex <- 0 until stages.length; stage = stages(stageIndex)){
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stage.inputs.keysIterator.foreach(key => inputOutputKeys.getOrElseUpdate(key,new KeyInfo).addInputStageIndex(stageIndex))
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stage.outputs.keysIterator.foreach(key => inputOutputKeys.getOrElseUpdate(key,new KeyInfo).addOutputStageIndex(stageIndex))
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}
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for((key,info) <- inputOutputKeys){
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//Interconnect inputs -> outputs
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for(stageIndex <- info.insertStageId to info.lastOutputStageId;
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stage = stages(stageIndex)) {
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stage.output(key)
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val outputDefault = stage.outputsDefault.getOrElse(key, null)
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if (outputDefault != null) {
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if (stageIndex == info.insertStageId) {
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outputDefault := stage.inserts(key)
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} else {
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outputDefault := stage.input(key)
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}
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}
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}
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//Interconnect outputs -> inputs
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for(stageIndex <- info.insertStageId + 1 to info.lastInputStageId) {
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val stageBefore = stages(stageIndex - 1)
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val stage = stages(stageIndex)
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stage.input(key)
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val inputDefault = stage.inputsDefault.getOrElse(key, null)
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if (inputDefault != null) {
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inputDefault := RegNextWhen(stageBefore.output(key),!stageBefore.arbitration.isStuck) //!stage.input.valid || stage.input.ready
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}
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}
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//Arbitration
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for(stageIndex <- 0 until stages.length; stage = stages(stageIndex)){
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stage.arbitration.isStuck := stages.takeRight(stages.length - stageIndex).map(_.arbitration.haltIt).reduce(_ || _)
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stage.arbitration.isFiring := stage.arbitration.isValid && !stage.arbitration.isStuck && !stage.arbitration.removeIt
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}
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for(stageIndex <- 1 until stages.length){
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val stageBefore = stages(stageIndex - 1)
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val stage = stages(stageIndex)
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stage.arbitration.isStuck := stages.takeRight(stages.length-stageIndex).map(_.arbitration.haltIt).reduce(_ || _)
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when(!stageBefore.arbitration.isStuck) {
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stage.arbitration.isValid := stage.arbitration.isValid && !stage.arbitration.removeIt
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}
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when(stage.arbitration.removeIt){
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stage.arbitration.isValid := False
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}
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}
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}
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}
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Component.current.addPrePopTask(() => build())
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}
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package SpinalRiscv
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import spinal.core.Area
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/**
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* Created by PIC32F_USER on 03/03/2017.
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*/
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trait Plugin[T <: Pipeline] {
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def getName() = this.getClass.getSimpleName.replace("$","")
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def setup(pipeline: T) : Unit = {}
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def build(pipeline: T) : Unit
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implicit class implicits(stage: Stage){
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def plug(area : Area) = area.setCompositeName(stage,getName()).reflectNames()
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}
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}
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@ -0,0 +1,73 @@
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package SpinalRiscv
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import spinal.core._
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import spinal.lib._
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import scala.collection.mutable
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class Stageable[T <: Data](dataType : T) extends HardType[T](dataType) with Nameable{
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setWeakName(this.getClass.getSimpleName.replace("$",""))
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}
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class Stage() extends Area{
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def input[T <: Data](key : Stageable[T]) : T = {
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inputs.getOrElseUpdate(key.asInstanceOf[Stageable[Data]],{
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val input,inputDefault = key()
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inputsDefault(key.asInstanceOf[Stageable[Data]]) = inputDefault
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input := inputDefault
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input.setPartialName(this,"input_" + key.getName())
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}).asInstanceOf[T]
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}
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def output[T <: Data](key : Stageable[T]) : T = {
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outputs.getOrElseUpdate(key.asInstanceOf[Stageable[Data]],{
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val output,outputDefault = key()
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outputsDefault(key.asInstanceOf[Stageable[Data]]) = outputDefault
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output := outputDefault
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output.setPartialName(this,"output_" + key.getName())
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}).asInstanceOf[T]
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}
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def insert[T <: Data](key : Stageable[T]) : T = inserts.getOrElseUpdate(key.asInstanceOf[Stageable[Data]],key()).asInstanceOf[T].setPartialName(this,key.getName())
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def apply[T <: Data](key : Stageable[T]) : T = ???
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val arbitration = new Bundle{
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val haltIt = False
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val removeIt = False
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val isValid = RegInit(False)
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val isStuck = Bool
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val isFiring = Bool
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}
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val inputs = mutable.HashMap[Stageable[Data],Data]()
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val outputs = mutable.HashMap[Stageable[Data],Data]()
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val signals = mutable.HashMap[Stageable[Data],Data]()
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val inserts = mutable.HashMap[Stageable[Data],Data]()
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val inputsDefault = mutable.HashMap[Stageable[Data],Data]()
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val outputsDefault = mutable.HashMap[Stageable[Data],Data]()
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}
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//object StageMain{
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//
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// object OpEnum extends SpinalEnum{
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// val AND,OR = newElement()
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// }
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// object OP extends Stageable(OpEnum())
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// object SRC1 extends Stageable(Bits(32 bits))
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// object SRC2 extends Stageable(Bits(32 bits))
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// object RESULT extends Stageable(Bits(32 bits))
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// def main(args: Array[String]) {
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// val E = List.fill(2)(new Stage(9))
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// val E0 = E(0)
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// import E0._
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// output(RESULT) := E(0).input(OP).mux(
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// OpEnum.AND -> (E(0).input(SRC1) & E(0).input(SRC2)),
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// OpEnum.OR -> (E(0).input(SRC1) | E(0).input(SRC2))
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// )
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// }
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//}
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@ -0,0 +1,170 @@
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/*
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* SpinalHDL
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* Copyright (c) Dolu, All rights reserved.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 3.0 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library.
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*/
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package SpinalRiscv
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import spinal.core._
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import spinal.lib._
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import scala.collection.mutable.ArrayBuffer
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object StandardStageables{
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object Execute0Bypass extends Stageable(Bool)
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object Execute1Bypass extends Stageable(Bool)
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object SRC1 extends Stageable(UInt(32 bits))
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object SRC2 extends Stageable(UInt(32 bits))
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object RESULT extends Stageable(UInt(32 bits))
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object PC extends Stageable(UInt())
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object INST extends Stageable(Bits(32 bits))
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}
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class SpinalRiscv(pluginConfig : Seq[Plugin[SpinalRiscv]]) extends Component with Pipeline{
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type T = SpinalRiscv
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stages ++= List.fill(6)(new Stage())
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val prefetch :: fetch :: decode :: execute :: memory :: writeBack :: Nil = stages.toList
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plugins ++= pluginConfig
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}
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trait DecoderService{
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def add(key : MaskedLiteral,values : Seq[(Stageable[_],BaseType)])
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def add(encoding :Seq[(MaskedLiteral,Seq[(Stageable[_],BaseType)])])
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}
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class DecoderSimplePlugin extends Plugin[SpinalRiscv] with DecoderService {
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override def add(encoding: Seq[(MaskedLiteral, Seq[(Stageable[_], BaseType)])]): Unit = encoding.foreach(e => this.add(e._1,e._2))
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override def add(key: MaskedLiteral, values: Seq[(Stageable[_], BaseType)]): Unit = {
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???
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}
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override def build(pipeline: SpinalRiscv): Unit = ???
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}
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trait PcManagerService{
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def jumpTo(pc : UInt,cond : Bool,stage : Stage) : Unit
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}
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class PcManagerSimplePlugin(resetVector : BigInt,pcWidth : Int,fastFetchCmdPcCalculation : Boolean) extends Plugin[SpinalRiscv] with PcManagerService{
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||||
import StandardStageables._
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|
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//FetchService interface
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case class JumpInfo(pc: UInt, cond: Bool, stage: Stage)
|
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val jumpInfos = ArrayBuffer[JumpInfo]()
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||||
override def jumpTo(pc: UInt, cond: Bool, stage: Stage): Unit = jumpInfos += JumpInfo(pc,cond,stage)
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||||
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||||
|
||||
override def build(pipeline: SpinalRiscv): Unit = {
|
||||
import pipeline.prefetch
|
||||
|
||||
prefetch.plug(new Area {
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||||
import prefetch._
|
||||
//Stage always valid
|
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arbitration.isValid := True
|
||||
|
||||
//PC calculation without Jump
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val pc = Reg(UInt(pcWidth bits)) init(resetVector)
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when(arbitration.isValid && !arbitration.isStuck){
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val pcPlus4 = pc + 4
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if(fastFetchCmdPcCalculation) pcPlus4.addAttribute("keep") //Disallow to use the carry in as enable
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pc := pcPlus4
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}
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|
||||
//FetchService hardware implementation
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||||
val jump = if(jumpInfos.length != 0) {
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val sortedByStage = jumpInfos.sortWith((a, b) => pipeline.indexOf(a.stage) > pipeline.indexOf(b.stage))
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val valids = sortedByStage.map(_.cond)
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val pcs = sortedByStage.map(_.pc)
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val pcLoad = Flow(UInt(pcWidth bits))
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pcLoad.valid := jumpInfos.foldLeft(False)(_ || _.cond)
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pcLoad.payload := MuxOH(valids, pcs)
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||||
//Register managments
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||||
when(pcLoad.valid) {
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||||
pc := pcLoad.payload
|
||||
arbitration.removeIt := True
|
||||
}
|
||||
}
|
||||
|
||||
//Pipeline insertions
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||||
insert(PC) := pc
|
||||
})
|
||||
}
|
||||
}
|
||||
|
||||
case class IBusSimpleCmd() extends Bundle{
|
||||
val pc = UInt(32 bits)
|
||||
}
|
||||
|
||||
case class IBusSimpleRsp() extends Bundle{
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||||
val inst = Bits(32 bits)
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||||
}
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||||
|
||||
class IBusSimplePlugin extends Plugin[SpinalRiscv]{
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||||
import StandardStageables._
|
||||
var iCmd : Stream[IBusSimpleCmd] = null
|
||||
var iRsp : IBusSimpleRsp = null
|
||||
|
||||
override def build(pipeline: SpinalRiscv): Unit = {
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import pipeline._
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||||
|
||||
iCmd = master(Stream(IBusSimpleCmd()))
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||||
iCmd.valid := prefetch.arbitration.isFiring
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iCmd.pc := prefetch.output(PC)
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||||
|
||||
iRsp = IBusSimpleRsp()
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||||
fetch.insert(INST) := iRsp.inst
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||||
}
|
||||
}
|
||||
|
||||
class IntAluPlugin extends Plugin[SpinalRiscv]{
|
||||
import StandardStageables._
|
||||
|
||||
|
||||
override def setup(pipeline: SpinalRiscv): Unit = {
|
||||
pipeline.service(classOf[DecoderService]).add(List(
|
||||
M"0101010---" ->
|
||||
List(
|
||||
Execute0Bypass -> True,
|
||||
Execute1Bypass -> True
|
||||
)
|
||||
)
|
||||
)
|
||||
}
|
||||
|
||||
override def build(pipeline: SpinalRiscv): Unit = {
|
||||
import pipeline._
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
||||
object MyTopLevel {
|
||||
def main(args: Array[String]) {
|
||||
SpinalVhdl(new SpinalRiscv(List(
|
||||
// new IntAluPlugin
|
||||
new PcManagerSimplePlugin(0,32,true),
|
||||
new IBusSimplePlugin
|
||||
)))
|
||||
}
|
||||
}
|
||||
|
||||
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