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Murax on arty_a7: fix RAMB type on soc_mmi.tcl

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japm48 2020-02-11 18:49:56 +01:00 committed by GitHub
parent ee36c36fdd
commit 163611bd11
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1 changed files with 2 additions and 2 deletions
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scripts/Murax/arty_a7/soc_mmi.tcl
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@ -21,7 +21,7 @@ proc swap_bits { bit } {
# open_run impl_1 # open_run impl_1
# Find all the RAMs, place in a list # Find all the RAMs, place in a list
set rams [get_cells -hier -regexp {.*core/system_ram/.*} -filter {REF_NAME =~ RAMB36E1}] set rams [get_cells -hier -regexp {.*core/system_ram/.*} -filter {REF_NAME == RAMB36E1 || REF_NAME == RAMB18E1}]
puts "[llength $rams] RAMs in total" puts "[llength $rams] RAMs in total"
foreach m $rams {puts $m} foreach m $rams {puts $m}
@ -89,7 +89,7 @@ set i 0
foreach ram $rams { foreach ram $rams {
# Get the RAM location # Get the RAM location
set loc_val [get_property LOC [get_cells $ram]] set loc_val [get_property LOC [get_cells $ram]]
regexp -- {(RAMB36_)([0-9XY]+)} $loc_val full ram_name loc_xy regexp {(RAMB.+_)([0-9XY]+)} $loc_val full ram_name loc_xy
set memi [dict create ram $ram loc $loc_xy] set memi [dict create ram $ram loc $loc_xy]