Hardware
/
VexRiscv
mirror of https://github.com/SpinalHDL/VexRiscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

DataCache.toBmb with aggregation sync path pipelined

This commit is contained in:
Dolu1990 2021-02-16 14:17:21 +01:00
parent fe690528f7
commit 1752b9e6d6
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/vexriscv/ip/DataCache.scala
View File

@ -489,7 +489,7 @@ case class DataCacheMemBus(p : DataCacheConfig) extends Bundle with IMasterSlave
cmdCtx.payload := aggregationCounter cmdCtx.payload := aggregationCounter
halt setWhen(!cmdCtx.ready) halt setWhen(!cmdCtx.ready)
val syncCtx = cmdCtx.queue(syncPendingMax) val syncCtx = cmdCtx.queue(syncPendingMax).s2mPipe().m2sPipe() //Assume latency of sync is at least 3 cycles
syncCtx.ready := bus.sync.fire syncCtx.ready := bus.sync.fire
sync.arbitrationFrom(bus.sync) sync.arbitrationFrom(bus.sync)