Merge pull request #1 from sebastien-riou/VXIP

Murax_xip: better pin names in scala, bootloader without magic word

scripts/Murax/iCE40-hx8k_breakout_board_xip/Murax_iCE40_hx8k_breakout_board_xip.pcf

@@ -1,12 +1,12 @@
 ## iCE40-hx8k breakout board
 
-set_io io_J3  J3
-set_io io_H16 H16
-set_io io_G15 G15
-set_io io_G16 G16
-set_io io_F15 F15
-set_io io_B12 B12
-set_io io_B10 B10
+set_io io_mainClk  J3
+set_io io_jtag_tck H16
+set_io io_jtag_tdi G15
+set_io io_jtag_tdo G16
+set_io io_jtag_tms F15
+set_io io_uart_txd B12
+set_io io_uart_rxd B10
 set_io io_led[0] B5
 set_io io_led[1] B4
 set_io io_led[2] A2
@@ -17,7 +17,7 @@ set_io io_led[6] B3
 set_io io_led[7] C3
 
 #XIP
-set_io io_P12 P12
-set_io io_P11 P11
-set_io io_R11 R11
-set_io io_R12 R12
+set_io io_miso P12
+set_io io_mosi P11
+set_io io_sclk R11
+set_io io_spis R12

scripts/Murax/iCE40-hx8k_breakout_board_xip/README.md

@@ -11,9 +11,8 @@ by the IceStorm
 
 # Bootloader operations
 
-A bootloader is implemented in a ROM within the FPGA bitfile. It configure the SPI and attempt to read the first word in 'XIP' area of the flash (0xE0040000 in CPU address space, 0x40000 in flash). If this first word is the magic word
+A bootloader is implemented in a ROM within the FPGA bitfile. It configure the SPI and attempt to read the first word in 'XIP' area of the flash (0xE0040000 in CPU address space, 0x40000 in flash). If this first word is not 0xFFFFFFFF and the same value is read 3 times,
 then the bootloader jump at 0xE0040000.
-The magic word is 0x12340fb7, which is the value for the instruction "li x31, 0x12340000" or "lui t6,0x12340".
 
 # Using the example
 

src/main/c/murax/xipBootloader/crt.S

@@ -43,9 +43,17 @@ crtStart:
   sw t0, CTRL_XIP_CONFIG(CTRL)
   li t0, XIP_BASE
   lw t1, (t0)
-  li t2, 0x12340fb7
-  xor t1,t1,t2
-  bnez t1,retry
+  li t2, 0xFFFFFFFF
+  xor t3,t1,t2
+  beqz t3,retry
+  //if we are here we have read a value from flash which is not all ones
+  lw t2, (t0)
+  xor t3,t1,t2
+  bnez t3,retry
+  lw t2, (t0)
+  xor t3,t1,t2
+  bnez t3,retry
+  //if we are here we have read the same value 3 times, so flash seems good, lets's jump
   jr t0
 
 retry:

src/main/scala/vexriscv/demo/Murax.scala

@@ -368,58 +368,55 @@ object Murax_iCE40_hx8k_breakout_board_xip{
 
   case class Murax_iCE40_hx8k_breakout_board_xip() extends Component{
     val io = new Bundle {
-      val J3  = in  Bool()
-      val H16 = in  Bool()
-      val G15 = in  Bool()
-      val G16 = out Bool()
-      val F15 = in  Bool()
-      val B12 = out Bool()
-      val B10 = in  Bool()
+      val mainClk  = in  Bool()
+      val jtag_tck = in  Bool()
+      val jtag_tdi = in  Bool()
+      val jtag_tdo = out Bool()
+      val jtag_tms = in  Bool()
+      val uart_txd = out Bool()
+      val uart_rxd = in  Bool()
 
-
-      //p12 as mosi mean flash config
-      val P12 = inout(Analog(Bool))
-      val P11 = inout(Analog(Bool))
-      val R11 = out Bool()
-      val R12 = out Bool()
+      val mosi = inout(Analog(Bool))
+      val miso = inout(Analog(Bool))
+      val sclk = out Bool()
+      val spis = out Bool()
 
       val led = out Bits(8 bits)
     }
-    //val murax = Murax(MuraxConfig.default(withXip = true))
     val murax = Murax(MuraxConfig.default(withXip = true).copy(onChipRamSize = 8 kB))
     murax.io.asyncReset := False
 
     val mainClkBuffer = SB_GB()
-    mainClkBuffer.USER_SIGNAL_TO_GLOBAL_BUFFER <> io.J3
+    mainClkBuffer.USER_SIGNAL_TO_GLOBAL_BUFFER <> io.mainClk
     mainClkBuffer.GLOBAL_BUFFER_OUTPUT <> murax.io.mainClk
 
     val jtagClkBuffer = SB_GB()
-    jtagClkBuffer.USER_SIGNAL_TO_GLOBAL_BUFFER <> io.H16
+    jtagClkBuffer.USER_SIGNAL_TO_GLOBAL_BUFFER <> io.jtag_tck
     jtagClkBuffer.GLOBAL_BUFFER_OUTPUT <> murax.io.jtag.tck
 
     io.led <> murax.io.gpioA.write(7 downto 0)
 
-    murax.io.jtag.tdi <> io.G15
-    murax.io.jtag.tdo <> io.G16
-    murax.io.jtag.tms <> io.F15
+    murax.io.jtag.tdi <> io.jtag_tdi
+    murax.io.jtag.tdo <> io.jtag_tdo
+    murax.io.jtag.tms <> io.jtag_tms
     murax.io.gpioA.read <> 0
-    murax.io.uart.txd <> io.B12
-    murax.io.uart.rxd <> io.B10
+    murax.io.uart.txd <> io.uart_txd
+    murax.io.uart.rxd <> io.uart_rxd
 
 
 
     val xip = new ClockingArea(murax.systemClockDomain) {
-      RegNext(murax.io.xip.ss.asBool) <> io.R12
+      RegNext(murax.io.xip.ss.asBool) <> io.spis
 
       val sclkIo = SB_IO_SCLK()
-      sclkIo.PACKAGE_PIN <> io.R11
+      sclkIo.PACKAGE_PIN <> io.sclk
       sclkIo.CLOCK_ENABLE := True
 
       sclkIo.OUTPUT_CLK := ClockDomain.current.readClockWire
       sclkIo.D_OUT_0 <> murax.io.xip.sclk.write(0)
       sclkIo.D_OUT_1 <> RegNext(murax.io.xip.sclk.write(1))
 
-      val datas = for ((data, pin) <- (murax.io.xip.data, List(io.P12, io.P11).reverse).zipped) yield new Area {
+      val datas = for ((data, pin) <- (murax.io.xip.data, List(io.mosi, io.miso)).zipped) yield new Area {
         val dataIo = SB_IO_DATA()
         dataIo.PACKAGE_PIN := pin
         dataIo.CLOCK_ENABLE := True