fpu added proper rounding for add (need to manage substraction)
This commit is contained in:
Dolu1990
parent
195e4c422d
commit
1ae84ea83b
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@ -30,6 +30,7 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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val rd = p.rfAddress()
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val value = Bits(32 bits)
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val arg = p.Arg()
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val roundMode = FpuRoundMode()
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}
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case class RfReadOutput() extends Bundle{
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@ -40,6 +41,7 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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val rd = p.rfAddress()
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val value = Bits(32 bits)
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val arg = p.Arg()
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val roundMode = FpuRoundMode()
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}
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@ -49,6 +51,7 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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val lockId = lockIdType()
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val i2f = Bool()
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val arg = Bits(2 bits)
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val roundMode = FpuRoundMode()
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}
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case class ShortPipInput() extends Bundle{
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@ -61,6 +64,7 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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val value = Bits(32 bits)
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val arg = Bits(2 bits)
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def rs1 = rs1Raw.as(p.internalFloating)
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val roundMode = FpuRoundMode()
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}
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case class MulInput() extends Bundle{
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@ -71,6 +75,7 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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val add = Bool()
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val divSqrt = Bool()
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val msb1, msb2 = Bool() //allow usage of msb bits of mul
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val roundMode = FpuRoundMode()
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}
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@ -80,6 +85,7 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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val rd = p.rfAddress()
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val lockId = lockIdType()
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val div = Bool()
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val roundMode = FpuRoundMode()
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}
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@ -88,16 +94,26 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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val rs1, rs2 = p.internalFloating()
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val rd = p.rfAddress()
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val lockId = lockIdType()
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val roundMode = FpuRoundMode()
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}
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case class WriteInput() extends Bundle{
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case class MergeInput() extends Bundle{
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val source = Source()
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val lockId = lockIdType()
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val rd = p.rfAddress()
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val value = p.internalFloating()
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val round = UInt(2 bits)
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val roundMode = FpuRoundMode()
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}
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case class RoundOutput() extends Bundle{
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val source = Source()
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val lockId = lockIdType()
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val rd = p.rfAddress()
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val value = p.internalFloating()
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}
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val rf = new Area{
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val ram = Mem(p.internalFloating, 32*portCount)
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val lock = for(i <- 0 until rfLockCount) yield new Area{
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@ -222,6 +238,7 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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output.lockId := s1LockId
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output.value := s1.value
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output.arg := s1.arg
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output.roundMode := s1.roundMode
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output.rd := s1.rd
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output.rs1 := rf.ram.readSync(s0.source @@ s0.rs1,enable = !output.isStall)
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output.rs2 := rf.ram.readSync(s0.source @@ s0.rs2,enable = !output.isStall)
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@ -298,6 +315,7 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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val value = p.storeLoadType()
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val i2f = Bool()
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val arg = Bits(2 bits)
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val roundMode = FpuRoundMode()
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}
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val s0 = new Area{
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@ -315,6 +333,7 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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output.value := feed.value
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output.i2f := input.i2f
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output.arg := input.arg
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output.roundMode := input.roundMode
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}
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@ -406,17 +425,20 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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when(isInfinity){recoded.setInfinity}
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when(isNan){recoded.setNan}
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val output = input.haltWhen(busy).swapPayload(WriteInput())
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val output = input.haltWhen(busy).swapPayload(MergeInput())
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output.source := input.source
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output.lockId := input.lockId
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output.roundMode := input.roundMode
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output.rd := input.rd
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output.value := recoded
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output.round := 0
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when(input.i2f){
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output.value.sign := i2fSign
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output.value.exponent := (U(exponentOne+31) - fsm.manTop).resized
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output.value.mantissa := U(i2fShifted)
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output.value.setNormal
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when(fsm.i2fZero) { output.value.setZero }
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//TODO ROUND
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}
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}
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}
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@ -424,7 +446,7 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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val shortPip = new Area{
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val input = decode.shortPip.stage()
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val rfOutput = Stream(WriteInput())
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val rfOutput = Stream(MergeInput())
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val result = p.storeLoadType().assignDontCare()
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@ -563,6 +585,8 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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rfOutput.source := input.source
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rfOutput.lockId := input.lockId
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rfOutput.rd := input.rd
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rfOutput.roundMode := input.roundMode
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rfOutput.round := 0 //TODO
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rfOutput.value.assignDontCare()
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switch(input.opcode){
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is(FpuOpcode.MIN_MAX){
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@ -634,11 +658,13 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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output.payload := math.mulC(p.internalMantissaSize, p.internalMantissaSize+1 bits)
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}
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val output = Stream(WriteInput())
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val output = Stream(MergeInput())
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output.valid := input.valid && !input.add && !input.divSqrt
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output.source := input.source
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output.lockId := input.lockId
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output.rd := input.rd
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output.roundMode := input.roundMode
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output.round := 0 //TODO
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output.value := norm.output
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decode.mulToAdd.valid := input.valid && input.add
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@ -650,6 +676,7 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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decode.mulToAdd.rs2 := input.rs3
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decode.mulToAdd.rd := input.rd
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decode.mulToAdd.lockId := input.lockId
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decode.mulToAdd.roundMode := input.roundMode
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input.ready := (input.add ? decode.mulToAdd.ready | output.ready) || input.divSqrt
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}
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@ -681,6 +708,7 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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decode.divSqrtToMul.msb2 := True
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decode.divSqrtToMul.rs1.special := False //TODO
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decode.divSqrtToMul.rs2.special := False
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decode.divSqrtToMul.roundMode := input.roundMode
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val aprox = new Area {
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@ -845,7 +873,8 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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val rs1MantissaBigger = input.rs1.mantissa > input.rs2.mantissa
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val absRs1Bigger = ((rs1ExponentBigger || rs1ExponentEqual && rs1MantissaBigger) && !input.rs1.isZero || input.rs1.isInfinity) && !input.rs2.isInfinity
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val shiftBy = rs1ExponentBigger ? (0-exp21) | exp21
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val passThrough = shiftBy >= p.internalMantissaSize || (input.rs1.isZero) || (input.rs2.isZero)
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val shiftOverflow = shiftBy >= p.internalMantissaSize
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val passThrough = shiftOverflow || (input.rs1.isZero) || (input.rs2.isZero)
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//Note that rs1ExponentBigger can be replaced by absRs1Bigger bellow to avoid xsigned two complement in math block at expense of combinatorial path
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val xySign = absRs1Bigger ? input.rs1.sign | input.rs2.sign
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@ -853,7 +882,14 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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val ySign = xySign ^ (rs1ExponentBigger ? input.rs2.sign | input.rs1.sign)
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val xMantissa = U"1" @@ (rs1ExponentBigger ? input.rs1.mantissa | input.rs2.mantissa) @@ U"0"
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val yMantissaUnshifted = U"1" @@ (rs1ExponentBigger ? input.rs2.mantissa | input.rs1.mantissa) @@ U"0"
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val yMantissa = yMantissaUnshifted >> (passThrough.asUInt @@ shiftBy.resize(log2Up(p.internalMantissaSize)))
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var yMantissa = yMantissaUnshifted
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val roundingScrap = CombInit(shiftOverflow)
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for(i <- 0 until log2Up(p.internalMantissaSize)){
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roundingScrap setWhen(shiftBy(i) && yMantissa(0, 1 << i bits) =/= 0)
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yMantissa \= shiftBy(i) ? (yMantissa |>> (BigInt(1) << i)) | yMantissa
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}
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when(passThrough) { yMantissa := 0 }
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// val yMantissa = yMantissaUnshifted >> (passThrough.asUInt @@ shiftBy.resize(log2Up(p.internalMantissaSize))) //Maybe passThrough.asUInt @@ do not infer small logic
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val xyExponent = rs1ExponentBigger ? input.rs1.exponent | input.rs2.exponent
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}
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@ -866,9 +902,9 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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def xySign = shifter.xySign
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val xSigned = xMantissa.twoComplement(xSign)
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// val ySigned = (yMantissa +^ (yMantissa.lsb && !ySign).asUInt).twoComplement(ySign)
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val ySigned = ((ySign ## Mux(ySign, ~yMantissa, yMantissa)).asUInt +^ (ySign || yMantissa.lsb).asUInt).asSInt //rounding here
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val xyMantissa = U(xSigned + ySigned).trim(1 bits)
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val ySigned = yMantissa.twoComplement(ySign)
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// val ySigned = ((ySign ## Mux(ySign, ~yMantissa, yMantissa)).asUInt +^ (ySign || yMantissa.lsb).asUInt).asSInt //rounding here
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val xyMantissa = U(xSigned +^ ySigned).trim(1 bits)
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}
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val norm = new Area{
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@ -878,9 +914,7 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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val shiftOh = OHMasking.first(xyMantissa.asBools.reverse)
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val shift = OHToUInt(shiftOh)
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val mantissa = (xyMantissa |<< shift) >> 2
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// val mantissaShifted = (xyMantissa |<< shift)
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// val mantissa = ((xyMantissa ) >> 2) + U(xyMantissa(1))
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val mantissa = (xyMantissa |<< shift)
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val exponent = xyExponent -^ shift + 1
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xySign clearWhen(input.rs1.isZero && input.rs2.isZero)
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val forceZero = xyMantissa === 0 || exponent.msb || (input.rs1.isZero && input.rs2.isZero)
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@ -889,14 +923,16 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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}
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val output = input.swapPayload(WriteInput())
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val output = input.swapPayload(MergeInput())
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output.source := input.source
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output.lockId := input.lockId
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output.rd := input.rd
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output.value.sign := norm.xySign
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output.value.mantissa := norm.mantissa.resized
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output.value.mantissa := (norm.mantissa >> 2).resized
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output.value.exponent := norm.exponent.resized
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output.value.special := False
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output.roundMode := input.roundMode
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output.round := norm.mantissa(1 downto 0) | (U"0" @@ shifter.roundingScrap)
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when(norm.forceNan) {
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output.value.setNanQuiet
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@ -911,25 +947,59 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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}
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val write = new Area{
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val merge = new Area {
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val arbitrated = StreamArbiterFactory.lowerFirst.noLock.on(List(load.s1.output, add.output, mul.output, shortPip.rfOutput))
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val isCommited = rf.lock.map(_.commited).read(arbitrated.lockId)
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val commited = arbitrated.haltWhen(!isCommited).toFlow
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}
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for(i <- 0 until portCount){
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completion(i).increments += (RegNext(commited.fire && commited.source === i) init(False))
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val round = new Area{
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val input = merge.commited.combStage
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val mantissaIncrement = !input.value.special && input.roundMode.mux(
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FpuRoundMode.RNE -> (input.round(1) && (input.round(0) || input.value.mantissa.lsb)),
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FpuRoundMode.RTZ -> False,
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FpuRoundMode.RDN -> (input.round =/= 0 && input.value.sign),
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FpuRoundMode.RUP -> (input.round =/= 0 && !input.value.sign),
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FpuRoundMode.RMM -> (input.round(1))
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)
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val math = p.internalFloating()
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val adder = (input.value.exponent @@ input.value.mantissa) + U(mantissaIncrement)
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math.special := input.value.special
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math.sign := input.value.sign
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math.exponent := adder(p.internalMantissaSize, p.internalExponentSize bits)
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math.mantissa := adder(0, p.internalMantissaSize bits)
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val patched = CombInit(math)
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when(!input.value.special && math.exponent === exponentOne + 128){
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patched.setInfinity
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}
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when(commited.valid){
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for(i <- 0 until rfLockCount) when(commited.lockId === i){
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val output = input.swapPayload(RoundOutput())
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output.source := input.source
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output.lockId := input.lockId
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output.rd := input.rd
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output.value := patched
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}
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val writeback = new Area{
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val input = round.output.combStage
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for(i <- 0 until portCount){
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completion(i).increments += (RegNext(input.fire && input.source === i) init(False))
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}
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when(input.valid){
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for(i <- 0 until rfLockCount) when(input.lockId === i){
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rf.lock(i).valid := False
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}
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}
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val port = rf.ram.writePort
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port.valid := commited.valid && rf.lock.map(_.write).read(commited.lockId)
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port.address := commited.source @@ commited.rd
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port.data := commited.value
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port.valid := input.valid && rf.lock.map(_.write).read(input.lockId)
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port.address := input.source @@ input.rd
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port.data := input.value
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when(port.valid){
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assert(!(port.data.exponent === 0 && !port.data.special), "Special violation")
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@ -89,6 +89,21 @@ object FpuFormat extends SpinalEnum{
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val FLOAT, DOUBLE = newElement()
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}
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object FpuRoundMode extends SpinalEnum(defaultEncoding = binarySequential){
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val RNE, RTZ, RDN, RUP, RMM = newElement()
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}
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object FpuRoundModeInstr extends SpinalEnum(){
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val RNE, RTZ, RDN, RUP, RMM, DYN = newElement()
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defaultEncoding = SpinalEnumEncoding("opt")(
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RNE -> 0,
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RTZ -> 1,
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RDN -> 2,
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RUP -> 3,
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RMM -> 4,
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DYN -> 7
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)
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}
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case class FpuParameter( internalMantissaSize : Int,
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withDouble : Boolean){
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@ -120,6 +135,7 @@ case class FpuCmd(p : FpuParameter) extends Bundle{
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val rs1, rs2, rs3 = p.rfAddress()
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val rd = p.rfAddress()
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val format = p.Format()
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val roundMode = FpuRoundMode()
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}
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case class FpuCommit(p : FpuParameter) extends Bundle{
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@ -166,14 +166,18 @@ class FpuPlugin(externalFpu : Boolean = false,
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arbitration.haltItself setWhen(arbitration.isValid && input(FPU_ENABLE) && hazard)
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arbitration.haltItself setWhen(port.cmd.isStall)
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port.cmd.valid := arbitration.isValid && input(FPU_ENABLE) && !forked && !hazard
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port.cmd.opcode := input(FPU_OPCODE)
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port.cmd.arg := input(FPU_ARG)
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port.cmd.rs1 := ((input(FPU_OPCODE) === FpuOpcode.STORE) ? input(INSTRUCTION)(rs2Range).asUInt | input(INSTRUCTION)(rs1Range).asUInt)
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port.cmd.rs2 := input(INSTRUCTION)(rs2Range).asUInt
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port.cmd.rs3 := input(INSTRUCTION)(rs3Range).asUInt
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port.cmd.rd := input(INSTRUCTION)(rdRange).asUInt
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port.cmd.format := FpuFormat.FLOAT
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val iRoundMode = input(INSTRUCTION)(funct3Range)
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val roundMode = (input(INSTRUCTION)(funct3Range) === B"111") ? csr.rm | input(INSTRUCTION)(funct3Range)
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port.cmd.valid := arbitration.isValid && input(FPU_ENABLE) && !forked && !hazard
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port.cmd.opcode := input(FPU_OPCODE)
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port.cmd.arg := input(FPU_ARG)
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port.cmd.rs1 := ((input(FPU_OPCODE) === FpuOpcode.STORE) ? input(INSTRUCTION)(rs2Range).asUInt | input(INSTRUCTION)(rs1Range).asUInt)
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port.cmd.rs2 := input(INSTRUCTION)(rs2Range).asUInt
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port.cmd.rs3 := input(INSTRUCTION)(rs3Range).asUInt
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port.cmd.rd := input(INSTRUCTION)(rdRange).asUInt
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port.cmd.format := FpuFormat.FLOAT
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port.cmd.roundMode := roundMode.as(FpuRoundMode())
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insert(FPU_FORKED) := forked || port.cmd.fire
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@ -0,0 +1,50 @@
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#include <stdio.h>
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#include <stdint.h>
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#include <stdint.h>
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#include <jni.h>
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#include <softfloat.h>
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extern void miaou();
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//#include <fenv.h>
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//#pragma STDC FENV_ACCESS ON
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//int applyRounding(int rounding){
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// int ret = fegetround( );
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// switch(rounding){
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// case 0: fesetround(FE_TONEAREST); break;
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// case 1: fesetround(FE_TOWARDZERO); break;
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// case 2: fesetround(FE_DOWNWARD); break;
|
||||
// case 3: fesetround(FE_UPWARD); break;
|
||||
// }
|
||||
// return ret;
|
||||
//}
|
||||
// const int originalRounding = applyRounding(rounding);
|
||||
// fesetround(originalRounding);
|
||||
|
||||
void applyRounding(int rounding){
|
||||
switch(rounding){
|
||||
case 0: softfloat_roundingMode = 0; break;
|
||||
case 1: softfloat_roundingMode = 1; break;
|
||||
case 2: softfloat_roundingMode = 2; break;
|
||||
case 3: softfloat_roundingMode = 3; break;
|
||||
case 4: softfloat_roundingMode = 4; break;
|
||||
}
|
||||
}
|
||||
|
||||
#define API __attribute__((visibility("default")))
|
||||
|
||||
//float32_t toF32(float v){
|
||||
// float32_t x;
|
||||
// x.v = ;
|
||||
// return x;
|
||||
//}
|
||||
|
||||
#define toF32(v) (*((float32_t*)&v))
|
||||
#define fromF32(x) (*((float*)&(x.v)))
|
||||
|
||||
JNIEXPORT jfloat API JNICALL Java_vexriscv_ip_fpu_FpuMath_addF32(JNIEnv * env, jobject obj, jfloat a, jfloat b, jint rounding){
|
||||
applyRounding(rounding);
|
||||
float32_t v = f32_add(toF32(a), toF32(b));
|
||||
return fromF32(v);
|
||||
}
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
CODEABI_1.0 {
|
||||
global: FpuMath_*;
|
||||
local: *;
|
||||
}
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
package vexriscv.ip.fpu;
|
||||
|
||||
import java.io.File;
|
||||
|
||||
public class FpuMath {
|
||||
public native float addF32(float a, float b, int rounding);
|
||||
|
||||
static{
|
||||
System.load(new File("src/test/cpp/fpu/math/fpu_math.so").getAbsolutePath());
|
||||
}
|
||||
}
|
||||
|
|
@ -1,12 +1,16 @@
|
|||
package vexriscv.ip.fpu
|
||||
|
||||
import java.io.File
|
||||
import java.lang
|
||||
|
||||
import org.apache.commons.io.FileUtils
|
||||
import org.scalatest.FunSuite
|
||||
import spinal.core.SpinalEnumElement
|
||||
import spinal.core.sim._
|
||||
import spinal.lib.DoCmd
|
||||
import spinal.lib.experimental.math.Floating
|
||||
import spinal.lib.sim._
|
||||
import spinal.sim.Backend.{isMac, isWindows}
|
||||
|
||||
import scala.collection.mutable
|
||||
import scala.collection.mutable.ArrayBuffer
|
||||
|
|
@ -113,7 +117,7 @@ class FpuTest extends FunSuite{
|
|||
}
|
||||
}
|
||||
|
||||
def add(rd : Int, rs1 : Int, rs2 : Int): Unit ={
|
||||
def add(rd : Int, rs1 : Int, rs2 : Int, rounding : FpuRoundMode.E = FpuRoundMode.RNE): Unit ={
|
||||
cmdQueue += {cmd =>
|
||||
cmd.opcode #= cmd.opcode.spinalEnum.ADD
|
||||
cmd.rs1 #= rs1
|
||||
|
|
@ -121,6 +125,7 @@ class FpuTest extends FunSuite{
|
|||
cmd.rs3.randomize()
|
||||
cmd.rd #= rd
|
||||
cmd.arg #= 0
|
||||
cmd.roundMode #= rounding
|
||||
}
|
||||
commitQueue += {cmd =>
|
||||
cmd.write #= true
|
||||
|
|
@ -318,20 +323,21 @@ class FpuTest extends FunSuite{
|
|||
(Random.nextDouble() * (Math.pow(2.0, exp)) * (if(Random.nextBoolean()) -1.0 else 1.0)).toFloat
|
||||
}
|
||||
|
||||
def testAdd(a : Float, b : Float): Unit ={
|
||||
def testAdd(a : Float, b : Float, rounding : FpuRoundMode.E = FpuRoundMode.RNE): Unit ={
|
||||
val rs = new RegAllocator()
|
||||
val rs1, rs2, rs3 = rs.allocate()
|
||||
val rd = Random.nextInt(32)
|
||||
load(rs1, a)
|
||||
load(rs2, b)
|
||||
|
||||
add(rd,rs1,rs2)
|
||||
add(rd,rs1,rs2, rounding)
|
||||
storeFloat(rd){v =>
|
||||
val a_ = clamp(a)
|
||||
val b_ = clamp(b)
|
||||
val ref = clamp(a_ + b_)
|
||||
println(f"$a + $b = $v, $ref")
|
||||
assert(checkFloat(ref, v))
|
||||
val ref = Clib.math.addF32(a,b, rounding.position)
|
||||
println(f"${a}%.19f + $b%.19f = $v, $ref $rounding")
|
||||
println(f"${f2b(a).toHexString} + ${f2b(b).toHexString}")
|
||||
assert(checkFloatExact(ref, v))
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -547,6 +553,39 @@ class FpuTest extends FunSuite{
|
|||
val iSigned = iSmall ++ iSmall.map(-_) ++ iBigSigned
|
||||
|
||||
|
||||
val roundingModes = FpuRoundMode.elements
|
||||
def foreachRounding(body : FpuRoundMode.E => Unit): Unit ={
|
||||
for(rounding <- roundingModes){
|
||||
body(rounding)
|
||||
}
|
||||
}
|
||||
|
||||
//TODO test and fix a - b rounding
|
||||
foreachRounding(testAdd(1.0f, b2f(0x3f800001), _)) //1.00001
|
||||
foreachRounding(testAdd(4.0f, b2f(0x3f800001), _)) //1.00001
|
||||
for(_ <- 0 until 10000; a = randomFloat(); b = randomFloat()) foreachRounding(testAdd(a.abs, b.abs,_)) //TODO negative
|
||||
|
||||
|
||||
waitUntil(cmdQueue.isEmpty)
|
||||
dut.clockDomain.waitSampling(1000)
|
||||
simSuccess()
|
||||
|
||||
testAdd(b2f(0x3f800000), b2f(0x3f800000-1))
|
||||
testAdd(1.1f, 2.3f)
|
||||
testAdd(1.2f, -1.2f)
|
||||
testAdd(-1.2f, 1.2f)
|
||||
testAdd(0.0f, -1.2f)
|
||||
testAdd(-0.0f, -1.2f)
|
||||
testAdd(1.2f, -0f)
|
||||
testAdd(1.2f, 0f)
|
||||
testAdd(1.1f, Float.MinPositiveValue)
|
||||
|
||||
for(a <- fAll; _ <- 0 until 50) testAdd(a, randomFloat())
|
||||
for(b <- fAll; _ <- 0 until 50) testAdd(randomFloat(), b)
|
||||
for(a <- fAll; b <- fAll) testAdd(a, b)
|
||||
for(_ <- 0 until 1000) testAdd(randomFloat(), randomFloat())
|
||||
|
||||
|
||||
testLoadStore(1.17549435082e-38f)
|
||||
testLoadStore(1.4E-45f)
|
||||
testLoadStore(3.44383110592e-41f)
|
||||
|
|
@ -573,21 +612,6 @@ class FpuTest extends FunSuite{
|
|||
|
||||
|
||||
|
||||
testAdd(b2f(0x3f800000), b2f(0x3f800000-1))
|
||||
testAdd(1.1f, 2.3f)
|
||||
testAdd(1.2f, -1.2f)
|
||||
testAdd(-1.2f, 1.2f)
|
||||
testAdd(0.0f, -1.2f)
|
||||
testAdd(-0.0f, -1.2f)
|
||||
testAdd(1.2f, -0f)
|
||||
testAdd(1.2f, 0f)
|
||||
testAdd(1.1f, Float.MinPositiveValue)
|
||||
|
||||
for(a <- fAll; _ <- 0 until 50) testAdd(a, randomFloat())
|
||||
for(b <- fAll; _ <- 0 until 50) testAdd(randomFloat(), b)
|
||||
for(a <- fAll; b <- fAll) testAdd(a, b)
|
||||
for(_ <- 0 until 1000) testAdd(randomFloat(), randomFloat())
|
||||
|
||||
|
||||
|
||||
testLoadStore(1.2f)
|
||||
|
|
@ -796,3 +820,24 @@ class FpuTest extends FunSuite{
|
|||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
object Clib {
|
||||
val java_home = System.getProperty("java.home")
|
||||
assert(java_home != "" && java_home != null, "JAVA_HOME need to be set")
|
||||
val jdk = java_home.replace("/jre","").replace("\\jre","")
|
||||
val jdkIncludes = jdk + "/include"
|
||||
val flags = List("-fPIC", "-m64", "-shared", "-Wno-attributes") //-Wl,--whole-archive
|
||||
val os = new File("/media/data/open/SaxonSoc/berkeley-softfloat-3/build/Linux-x86_64-GCC").listFiles().map(_.getAbsolutePath).filter(_.toString.endsWith(".o"))
|
||||
val cmd = s"gcc -I/media/data/open/SaxonSoc/berkeley-softfloat-3/source/include -I$jdkIncludes -I$jdkIncludes/linux ${flags.mkString(" ")} -o src/test/cpp/fpu/math/fpu_math.so src/test/cpp/fpu/math/fpu_math.c src/test/cpp/fpu/math/softfloat.a" // src/test/cpp/fpu/math/softfloat.a
|
||||
DoCmd.doCmd(cmd)
|
||||
val math = new FpuMath
|
||||
}
|
||||
|
||||
object FpuCompileSo extends App{
|
||||
|
||||
println(Clib.math.addF32(1.00000011921f, 4.0f, FpuRoundMode.RNE.position))
|
||||
println(Clib.math.addF32(1.00000011921f, 4.0f, FpuRoundMode.RTZ.position))
|
||||
println(Clib.math.addF32(1.00000011921f, 4.0f, FpuRoundMode.RDN.position))
|
||||
println(Clib.math.addF32(1.00000011921f, 4.0f, FpuRoundMode.RUP.position))
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue