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https://github.com/SpinalHDL/VexRiscv.git
synced 2025-01-03 03:43:39 -05:00
Add GenTwoStage config and UltraScale synthesis
This commit is contained in:
Dolu1990
parent
861df664cf
commit
1d0e180e1d
3 changed files with 205 additions and 9 deletions
71
src/main/scala/vexriscv/demo/GenTwoStage.scala
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71
src/main/scala/vexriscv/demo/GenTwoStage.scala
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@ -0,0 +1,71 @@
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package vexriscv.demo
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import spinal.core.SpinalVerilog
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import vexriscv.{VexRiscv, VexRiscvConfig, plugin}
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import vexriscv.plugin.{BranchPlugin, CsrPlugin, CsrPluginConfig, DBusSimplePlugin, DecoderSimplePlugin, DivPlugin, FullBarrelShifterPlugin, HazardSimplePlugin, IBusSimplePlugin, IntAluPlugin, LightShifterPlugin, MulPlugin, MulSimplePlugin, NONE, RegFilePlugin, SrcPlugin, YamlPlugin}
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object GenTwoStage extends App{
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def cpu(withMulDiv : Boolean,
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bypass : Boolean,
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barrielShifter : Boolean) = new VexRiscv(
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config = VexRiscvConfig(
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withMemoryStage = false,
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withWriteBackStage = false,
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plugins = List(
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new IBusSimplePlugin(
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resetVector = 0x80000000l,
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cmdForkOnSecondStage = false,
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cmdForkPersistence = false,
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prediction = NONE,
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catchAccessFault = false,
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compressedGen = false,
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injectorStage = false
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),
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new DBusSimplePlugin(
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catchAddressMisaligned = false,
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catchAccessFault = false
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),
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new CsrPlugin(CsrPluginConfig.smallest),
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new DecoderSimplePlugin(
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catchIllegalInstruction = false
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),
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new RegFilePlugin(
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regFileReadyKind = plugin.SYNC,
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readInExecute = true,
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zeroBoot = true,
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x0Init = false
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),
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new IntAluPlugin,
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new SrcPlugin(
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separatedAddSub = false,
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executeInsertion = true
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),
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new HazardSimplePlugin(
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bypassExecute = bypass,
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bypassMemory = false,
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bypassWriteBack = false,
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bypassWriteBackBuffer = bypass,
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pessimisticUseSrc = false,
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pessimisticWriteRegFile = false,
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pessimisticAddressMatch = false
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),
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new BranchPlugin(
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earlyBranch = true,
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catchAddressMisaligned = false
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),
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new YamlPlugin("cpu0.yaml")
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) ++ (if(!withMulDiv) Nil else List(
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new MulSimplePlugin,
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new DivPlugin
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)) ++ List(if(!barrielShifter)
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new LightShifterPlugin
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else
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new FullBarrelShifterPlugin(
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earlyInjection = true
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)
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)
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)
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)
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SpinalVerilog(cpu(false,false,false))
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}
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@ -4,6 +4,7 @@ import spinal.core._
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import spinal.lib._
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import spinal.lib.eda.bench._
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import spinal.lib.eda.icestorm.IcestormStdTargets
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import spinal.lib.eda.xilinx.VivadoFlow
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import spinal.lib.io.InOutWrapper
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import vexriscv.VexRiscv
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import vexriscv.plugin.DecoderSimplePlugin
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@ -49,6 +50,42 @@ object VexRiscvSynthesisBench {
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// top
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// }
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val twoStage = new Rtl {
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override def getName(): String = "VexRiscv two stages"
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override def getRtlPath(): String = "VexRiscvTwoStages.v"
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SpinalVerilog(wrap(GenTwoStage.cpu(
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withMulDiv = false,
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bypass = false,
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barrielShifter = false
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)).setDefinitionName(getRtlPath().split("\\.").head))
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}
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val twoStageBarell = new Rtl {
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override def getName(): String = "VexRiscv two stages with barriel"
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override def getRtlPath(): String = "VexRiscvTwoStagesBar.v"
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SpinalVerilog(wrap(GenTwoStage.cpu(
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withMulDiv = false,
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bypass = true,
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barrielShifter = true
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)).setDefinitionName(getRtlPath().split("\\.").head))
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}
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val twoStageMulDiv = new Rtl {
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override def getName(): String = "VexRiscv two stages with Mul Div"
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override def getRtlPath(): String = "VexRiscvTwoStagesMD.v"
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SpinalVerilog(wrap(GenTwoStage.cpu(
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withMulDiv = true,
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bypass = false,
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barrielShifter = false
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)).setDefinitionName(getRtlPath().split("\\.").head))
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}
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val twoStageAll = new Rtl {
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override def getName(): String = "VexRiscv two stages with Mul Div fast"
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override def getRtlPath(): String = "VexRiscvTwoStagesMDfast.v"
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SpinalVerilog(wrap(GenTwoStage.cpu(
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withMulDiv = true,
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bypass = true,
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barrielShifter = true
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)).setDefinitionName(getRtlPath().split("\\.").head))
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}
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val smallestNoCsr = new Rtl {
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override def getName(): String = "VexRiscv smallest no CSR"
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override def getRtlPath(): String = "VexRiscvSmallestNoCsr.v"
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@ -109,13 +146,63 @@ object VexRiscvSynthesisBench {
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SpinalConfig(inlineRom = true).generateVerilog(wrap(new VexRiscv(LinuxGen.configFull(false, true))).setDefinitionName(getRtlPath().split("\\.").head))
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}
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val rtls = List(smallestNoCsr, smallest, smallAndProductive, smallAndProductiveWithICache, fullNoMmuNoCache, noCacheNoMmuMaxPerf, fullNoMmuMaxPerf, fullNoMmu, full, linuxBalanced)
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// val rtls = List(smallestNoCsr, smallest, smallAndProductive, smallAndProductiveWithICache)
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// val rtls = List(smallAndProductive, smallAndProductiveWithICache, fullNoMmuMaxPerf, fullNoMmu, full)
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// val rtls = List(smallAndProductive)
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val targets = XilinxStdTargets() ++ AlteraStdTargets() ++ IcestormStdTargets().take(1)
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val rtls = List(twoStage, twoStageBarell, twoStageMulDiv, twoStageAll, smallestNoCsr, smallest, smallAndProductive, smallAndProductiveWithICache, fullNoMmuNoCache, noCacheNoMmuMaxPerf, fullNoMmuMaxPerf, fullNoMmu, full, linuxBalanced)
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// val rtls = List(twoStage, twoStageBarell, twoStageMulDiv, twoStageAll)
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// val rtls = List(smallest)
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val targets = XilinxStdTargets() ++ AlteraStdTargets() ++ IcestormStdTargets().take(1) ++ List(
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new Target {
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override def getFamilyName(): String = "Kintex UltraScale"
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override def synthesise(rtl: Rtl, workspace: String): Report = {
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VivadoFlow(
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frequencyTarget = 50 MHz,
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vivadoPath=sys.env.getOrElse("VIVADO_ARTIX_7_BIN", null),
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workspacePath=workspace + "_area",
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toplevelPath=rtl.getRtlPath(),
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family=getFamilyName(),
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device="xcku035-fbva900-3-e"
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)
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}
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},
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new Target {
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override def getFamilyName(): String = "Kintex UltraScale"
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override def synthesise(rtl: Rtl, workspace: String): Report = {
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VivadoFlow(
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frequencyTarget = 800 MHz,
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vivadoPath=sys.env.getOrElse("VIVADO_ARTIX_7_BIN", null),
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workspacePath=workspace + "_fmax",
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toplevelPath=rtl.getRtlPath(),
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family=getFamilyName(),
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device="xcku035-fbva900-3-e"
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)
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}
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},
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new Target {
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override def getFamilyName(): String = "Kintex UltraScale+"
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override def synthesise(rtl: Rtl, workspace: String): Report = {
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VivadoFlow(
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frequencyTarget = 50 MHz,
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vivadoPath=sys.env.getOrElse("VIVADO_ARTIX_7_BIN", null),
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workspacePath=workspace + "_area",
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toplevelPath=rtl.getRtlPath(),
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family=getFamilyName(),
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device="xcku3p-ffvd900-3-e"
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)
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}
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},
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new Target {
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override def getFamilyName(): String = "Kintex UltraScale+"
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override def synthesise(rtl: Rtl, workspace: String): Report = {
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VivadoFlow(
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frequencyTarget = 800 MHz,
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vivadoPath=sys.env.getOrElse("VIVADO_ARTIX_7_BIN", null),
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workspacePath=workspace + "_fmax",
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toplevelPath=rtl.getRtlPath(),
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family=getFamilyName(),
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device="xcku3p-ffvd900-3-e"
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)
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}
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}
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)
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// val targets = IcestormStdTargets()
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Bench(rtls, targets)
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}
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@ -2,7 +2,8 @@ package vexriscv
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import java.io.File
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import org.scalatest.{FunSuite}
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import org.scalatest.FunSuite
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import spinal.core.SpinalVerilog
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import vexriscv.demo._
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import scala.sys.process._
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@ -42,6 +43,43 @@ class DhrystoneBench extends FunSuite{
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}
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getDmips(
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name = "GenTwoStageArty",
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gen = SpinalVerilog(GenTwoStage.cpu(
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withMulDiv = false,
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bypass = false,
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barrielShifter = false
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)),
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testCmd = "make clean run REDO=10 IBUS=SIMPLE DBUS=SIMPLE CSR=no MMU=no DEBUG_PLUGIN=no MUL=no DIV=no COREMARK=yes"
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)
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getDmips(
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name = "GenTwoStageBarrielArty",
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gen = SpinalVerilog(GenTwoStage.cpu(
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withMulDiv = false,
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bypass = true,
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barrielShifter = true
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)),
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testCmd = "make clean run REDO=10 IBUS=SIMPLE DBUS=SIMPLE CSR=no MMU=no DEBUG_PLUGIN=no MUL=no DIV=no COREMARK=yes"
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)
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getDmips(
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name = "GenTwoStageMDArty",
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gen = SpinalVerilog(GenTwoStage.cpu(
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withMulDiv = true,
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bypass = false,
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barrielShifter = false
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)),
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testCmd = "make clean run REDO=10 IBUS=SIMPLE DBUS=SIMPLE CSR=no MMU=no DEBUG_PLUGIN=no MUL=yes DIV=yes COREMARK=yes"
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)
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getDmips(
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name = "GenTwoStageMDBarrielArty",
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gen = SpinalVerilog(GenTwoStage.cpu(
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withMulDiv = true,
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bypass = true,
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barrielShifter = true
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)),
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testCmd = "make clean run REDO=10 IBUS=SIMPLE DBUS=SIMPLE CSR=no MMU=no DEBUG_PLUGIN=no MUL=yes DIV=yes COREMARK=yes"
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)
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getDmips(
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name = "GenSmallestNoCsr",
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gen = GenSmallestNoCsr.main(null),
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@ -104,7 +142,7 @@ class DhrystoneBench extends FunSuite{
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gen = LinuxGen.main(Array.fill[String](0)("")),
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testCmd = "make clean run IBUS=CACHED DBUS=CACHED DEBUG_PLUGIN=STD DHRYSTONE=yes SUPERVISOR=yes MMU=no CSR=yes CSR_SKIP_TEST=yes COMPRESSED=no MUL=yes DIV=yes LRSC=yes AMO=yes REDO=10 TRACE=no COREMARK=yes LINUX_REGRESSION=no"
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)
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//make run IBUS=CACHED DBUS=CACHED DEBUG_PLUGIN=STD DHRYSTONE=yess SUPERVISOR=yes CSR=yes COMPRESSED=no MUL=yes DIV=yes LRSC=yes AMO=yes REDO=1 TRACE=no LINUX_REGRESSION=yes SEED=42
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// //make run IBUS=CACHED DBUS=CACHED DEBUG_PLUGIN=STD DHRYSTONE=yess SUPERVISOR=yes CSR=yes COMPRESSED=no MUL=yes DIV=yes LRSC=yes AMO=yes REDO=1 TRACE=no LINUX_REGRESSION=yes SEED=42
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test("final_report") {
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