Add GenTwoStage config and UltraScale synthesis

src/main/scala/vexriscv/demo/GenTwoStage.scala

@@ -0,0 +1,71 @@
+package vexriscv.demo
+
+import spinal.core.SpinalVerilog
+import vexriscv.{VexRiscv, VexRiscvConfig, plugin}
+import vexriscv.plugin.{BranchPlugin, CsrPlugin, CsrPluginConfig, DBusSimplePlugin, DecoderSimplePlugin, DivPlugin, FullBarrelShifterPlugin, HazardSimplePlugin, IBusSimplePlugin, IntAluPlugin, LightShifterPlugin, MulPlugin, MulSimplePlugin, NONE, RegFilePlugin, SrcPlugin, YamlPlugin}
+
+object GenTwoStage extends App{
+  def cpu(withMulDiv : Boolean,
+          bypass : Boolean,
+          barrielShifter : Boolean) = new VexRiscv(
+    config = VexRiscvConfig(
+      withMemoryStage = false,
+      withWriteBackStage = false,
+      plugins = List(
+        new IBusSimplePlugin(
+          resetVector = 0x80000000l,
+          cmdForkOnSecondStage = false,
+          cmdForkPersistence = false,
+          prediction = NONE,
+          catchAccessFault = false,
+          compressedGen = false,
+          injectorStage = false
+        ),
+        new DBusSimplePlugin(
+          catchAddressMisaligned = false,
+          catchAccessFault = false
+        ),
+        new CsrPlugin(CsrPluginConfig.smallest),
+        new DecoderSimplePlugin(
+          catchIllegalInstruction = false
+        ),
+        new RegFilePlugin(
+          regFileReadyKind = plugin.SYNC,
+          readInExecute = true,
+          zeroBoot = true,
+          x0Init = false
+        ),
+        new IntAluPlugin,
+        new SrcPlugin(
+          separatedAddSub = false,
+          executeInsertion = true
+        ),
+        new HazardSimplePlugin(
+          bypassExecute           = bypass,
+          bypassMemory            = false,
+          bypassWriteBack         = false,
+          bypassWriteBackBuffer   = bypass,
+          pessimisticUseSrc       = false,
+          pessimisticWriteRegFile = false,
+          pessimisticAddressMatch = false
+        ),
+        new BranchPlugin(
+          earlyBranch = true,
+          catchAddressMisaligned = false
+        ),
+        new YamlPlugin("cpu0.yaml")
+      ) ++ (if(!withMulDiv) Nil else List(
+        new MulSimplePlugin,
+        new DivPlugin
+      )) ++ List(if(!barrielShifter)
+        new LightShifterPlugin
+      else
+        new FullBarrelShifterPlugin(
+          earlyInjection = true
+        )
+      )
+    )
+  )
+
+  SpinalVerilog(cpu(false,false,false))
+}

src/main/scala/vexriscv/demo/SynthesisBench.scala

@@ -4,6 +4,7 @@ import spinal.core._
 import spinal.lib._
 import spinal.lib.eda.bench._
 import spinal.lib.eda.icestorm.IcestormStdTargets
+import spinal.lib.eda.xilinx.VivadoFlow
 import spinal.lib.io.InOutWrapper
 import vexriscv.VexRiscv
 import vexriscv.plugin.DecoderSimplePlugin
@@ -49,6 +50,42 @@ object VexRiscvSynthesisBench {
 //      top
 //    }
 
+    val twoStage = new Rtl {
+      override def getName(): String = "VexRiscv two stages"
+      override def getRtlPath(): String = "VexRiscvTwoStages.v"
+      SpinalVerilog(wrap(GenTwoStage.cpu(
+        withMulDiv = false,
+        bypass = false,
+        barrielShifter = false
+      )).setDefinitionName(getRtlPath().split("\\.").head))
+    }
+    val twoStageBarell = new Rtl {
+      override def getName(): String = "VexRiscv two stages with barriel"
+      override def getRtlPath(): String = "VexRiscvTwoStagesBar.v"
+      SpinalVerilog(wrap(GenTwoStage.cpu(
+        withMulDiv = false,
+        bypass = true,
+        barrielShifter = true
+      )).setDefinitionName(getRtlPath().split("\\.").head))
+    }
+    val twoStageMulDiv = new Rtl {
+      override def getName(): String = "VexRiscv two stages with Mul Div"
+      override def getRtlPath(): String = "VexRiscvTwoStagesMD.v"
+      SpinalVerilog(wrap(GenTwoStage.cpu(
+        withMulDiv = true,
+        bypass = false,
+        barrielShifter = false
+      )).setDefinitionName(getRtlPath().split("\\.").head))
+    }
+    val twoStageAll = new Rtl {
+      override def getName(): String = "VexRiscv two stages with Mul Div fast"
+      override def getRtlPath(): String = "VexRiscvTwoStagesMDfast.v"
+      SpinalVerilog(wrap(GenTwoStage.cpu(
+        withMulDiv = true,
+        bypass = true,
+        barrielShifter = true
+      )).setDefinitionName(getRtlPath().split("\\.").head))
+    }
     val smallestNoCsr = new Rtl {
       override def getName(): String = "VexRiscv smallest no CSR"
       override def getRtlPath(): String = "VexRiscvSmallestNoCsr.v"
@@ -109,13 +146,63 @@ object VexRiscvSynthesisBench {
       SpinalConfig(inlineRom = true).generateVerilog(wrap(new VexRiscv(LinuxGen.configFull(false, true))).setDefinitionName(getRtlPath().split("\\.").head))
     }
 
-    val rtls = List(smallestNoCsr, smallest, smallAndProductive, smallAndProductiveWithICache, fullNoMmuNoCache, noCacheNoMmuMaxPerf, fullNoMmuMaxPerf, fullNoMmu, full, linuxBalanced)
+    val rtls = List(twoStage, twoStageBarell, twoStageMulDiv, twoStageAll, smallestNoCsr, smallest, smallAndProductive, smallAndProductiveWithICache, fullNoMmuNoCache, noCacheNoMmuMaxPerf, fullNoMmuMaxPerf, fullNoMmu, full, linuxBalanced)
-//    val rtls = List(smallestNoCsr, smallest, smallAndProductive, smallAndProductiveWithICache)
+//    val rtls = List(twoStage, twoStageBarell, twoStageMulDiv, twoStageAll)
-    //      val rtls = List(smallAndProductive, smallAndProductiveWithICache, fullNoMmuMaxPerf, fullNoMmu, full)
+//    val rtls = List(smallest)
-//    val rtls = List(smallAndProductive)
+    val targets = XilinxStdTargets() ++ AlteraStdTargets() ++  IcestormStdTargets().take(1)  ++ List(
-
+      new Target {
-    val targets = XilinxStdTargets() ++ AlteraStdTargets() ++  IcestormStdTargets().take(1)
+        override def getFamilyName(): String = "Kintex UltraScale"
-
+        override def synthesise(rtl: Rtl, workspace: String): Report = {
+          VivadoFlow(
+            frequencyTarget = 50 MHz,
+            vivadoPath=sys.env.getOrElse("VIVADO_ARTIX_7_BIN", null),
+            workspacePath=workspace + "_area",
+            toplevelPath=rtl.getRtlPath(),
+            family=getFamilyName(),
+            device="xcku035-fbva900-3-e"
+          )
+        }
+      },
+      new Target {
+        override def getFamilyName(): String = "Kintex UltraScale"
+        override def synthesise(rtl: Rtl, workspace: String): Report = {
+          VivadoFlow(
+            frequencyTarget = 800 MHz,
+            vivadoPath=sys.env.getOrElse("VIVADO_ARTIX_7_BIN", null),
+            workspacePath=workspace + "_fmax",
+            toplevelPath=rtl.getRtlPath(),
+            family=getFamilyName(),
+            device="xcku035-fbva900-3-e"
+          )
+        }
+      },
+      new Target {
+        override def getFamilyName(): String = "Kintex UltraScale+"
+        override def synthesise(rtl: Rtl, workspace: String): Report = {
+          VivadoFlow(
+            frequencyTarget = 50 MHz,
+            vivadoPath=sys.env.getOrElse("VIVADO_ARTIX_7_BIN", null),
+            workspacePath=workspace + "_area",
+            toplevelPath=rtl.getRtlPath(),
+            family=getFamilyName(),
+            device="xcku3p-ffvd900-3-e"
+          )
+        }
+      },
+      new Target {
+        override def getFamilyName(): String = "Kintex UltraScale+"
+        override def synthesise(rtl: Rtl, workspace: String): Report = {
+          VivadoFlow(
+            frequencyTarget = 800 MHz,
+            vivadoPath=sys.env.getOrElse("VIVADO_ARTIX_7_BIN", null),
+            workspacePath=workspace + "_fmax",
+            toplevelPath=rtl.getRtlPath(),
+            family=getFamilyName(),
+            device="xcku3p-ffvd900-3-e"
+          )
+        }
+      }
+    )
     //    val targets = IcestormStdTargets()
     Bench(rtls, targets)
   }

src/test/scala/vexriscv/DhrystoneBench.scala

@@ -2,7 +2,8 @@ package vexriscv
 
 import java.io.File
 
-import org.scalatest.{FunSuite}
+import org.scalatest.FunSuite
+import spinal.core.SpinalVerilog
 import vexriscv.demo._
 
 import scala.sys.process._
@@ -42,6 +43,43 @@ class DhrystoneBench extends FunSuite{
 
   }
 
+  getDmips(
+    name = "GenTwoStageArty",
+    gen = SpinalVerilog(GenTwoStage.cpu(
+      withMulDiv = false,
+      bypass = false,
+      barrielShifter = false
+    )),
+    testCmd = "make clean run REDO=10 IBUS=SIMPLE DBUS=SIMPLE CSR=no MMU=no DEBUG_PLUGIN=no MUL=no DIV=no  COREMARK=yes"
+  )
+  getDmips(
+    name = "GenTwoStageBarrielArty",
+    gen = SpinalVerilog(GenTwoStage.cpu(
+      withMulDiv = false,
+      bypass = true,
+      barrielShifter = true
+    )),
+    testCmd = "make clean run REDO=10 IBUS=SIMPLE DBUS=SIMPLE CSR=no MMU=no DEBUG_PLUGIN=no MUL=no DIV=no  COREMARK=yes"
+  )
+  getDmips(
+    name = "GenTwoStageMDArty",
+    gen = SpinalVerilog(GenTwoStage.cpu(
+      withMulDiv = true,
+      bypass = false,
+      barrielShifter = false
+    )),
+    testCmd = "make clean run REDO=10 IBUS=SIMPLE DBUS=SIMPLE CSR=no MMU=no DEBUG_PLUGIN=no MUL=yes DIV=yes  COREMARK=yes"
+  )
+  getDmips(
+    name = "GenTwoStageMDBarrielArty",
+    gen = SpinalVerilog(GenTwoStage.cpu(
+      withMulDiv = true,
+      bypass = true,
+      barrielShifter = true
+    )),
+    testCmd = "make clean run REDO=10 IBUS=SIMPLE DBUS=SIMPLE CSR=no MMU=no DEBUG_PLUGIN=no MUL=yes DIV=yes  COREMARK=yes"
+  )
+
   getDmips(
     name = "GenSmallestNoCsr",
     gen = GenSmallestNoCsr.main(null),
@@ -104,7 +142,7 @@ class DhrystoneBench extends FunSuite{
     gen = LinuxGen.main(Array.fill[String](0)("")),
     testCmd = "make clean run IBUS=CACHED DBUS=CACHED DEBUG_PLUGIN=STD DHRYSTONE=yes SUPERVISOR=yes MMU=no CSR=yes CSR_SKIP_TEST=yes  COMPRESSED=no MUL=yes DIV=yes LRSC=yes AMO=yes REDO=10 TRACE=no COREMARK=yes LINUX_REGRESSION=no"
   )
-  //make run  IBUS=CACHED DBUS=CACHED DEBUG_PLUGIN=STD DHRYSTONE=yess SUPERVISOR=yes CSR=yes COMPRESSED=no MUL=yes DIV=yes LRSC=yes AMO=yes REDO=1 TRACE=no LINUX_REGRESSION=yes SEED=42
+//  //make run  IBUS=CACHED DBUS=CACHED DEBUG_PLUGIN=STD DHRYSTONE=yess SUPERVISOR=yes CSR=yes COMPRESSED=no MUL=yes DIV=yes LRSC=yes AMO=yes REDO=1 TRACE=no LINUX_REGRESSION=yes SEED=42
 
 
   test("final_report") {