mirror of
https://github.com/SpinalHDL/VexRiscv.git
synced 2025-01-03 03:43:39 -05:00
fpu f2i rounding ok and full shifter
This commit is contained in:
Dolu1990
parent
ef011fa0d4
commit
1d0eecdcb0
3 changed files with 179 additions and 127 deletions
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@ -57,13 +57,11 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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case class ShortPipInput() extends Bundle{
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val source = Source()
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val opcode = p.Opcode()
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val rs2 = p.internalFloating()
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val rs1Raw = Bits(widthOf(rs2) bits)
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val rs1, rs2 = p.internalFloating()
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val lockId = lockIdType()
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val rd = p.rfAddress()
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val value = Bits(32 bits)
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val arg = Bits(2 bits)
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def rs1 = rs1Raw.as(p.internalFloating)
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val roundMode = FpuRoundMode()
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}
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@ -261,7 +259,6 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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input.ready setWhen(shortPipHit && shortPip.ready)
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shortPip.valid := input.valid && shortPipHit
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shortPip.payload.assignSomeByName(read.output.payload)
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shortPip.rs1Raw := read.output.rs1.asBits
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val divSqrtHit = input.opcode === p.Opcode.DIV || input.opcode === p.Opcode.SQRT
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val divSqrt = Stream(DivSqrtInput())
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@ -461,49 +458,46 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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val f2iShift = input.rs1.exponent - U(exponentOne)
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val isF2i = input.opcode === FpuOpcode.F2I
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val needRecoding = List(FpuOpcode.FMV_X_W, FpuOpcode.STORE).map(_ === input.opcode).orR && isSubnormal
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val manTop = Reg(UInt(log2Up(p.internalMantissaSize) bits))
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val counter = Reg(UInt(log2Up(p.internalMantissaSize+1) bits))
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val done, boot = Reg(Bool())
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val isZero = input.rs1.isZero// || input.rs1.exponent < exponentOne-1
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val overflow = input.rs1.exponent > (input.arg(0) ? U(exponentOne+30) | U(exponentOne+31)) && !input.rs1.sign
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val underflow = input.rs1.exponent > (input.arg(0) ? U(exponentOne+30) | U(exponentOne-1)) && input.rs1.sign // && !(input.arg(0) && input.rs1.exponent === exponentOne-31 && input.rs)
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val shift = new Area{
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val by = Reg(UInt(log2Up(p.internalMantissaSize max 33) bits))
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val input = UInt(p.internalMantissaSize max 33 bits).assignDontCare()
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var logic = input
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val scrap = Reg(Bool)
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for(i <- by.range){
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scrap setWhen(by(i) && logic(0, 1 << i bits) =/= 0)
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logic \= by(i) ? (logic |>> (BigInt(1) << i)) | logic
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}
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when(boot){
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scrap := False
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}
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val output = RegNextWhen(logic, !done)
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}
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shift.input := (U(!isZero) @@ input.rs1.mantissa) << 9
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when(input.valid && (needRecoding || isF2i) && !done){
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halt := True
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when(boot){
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when(isF2i){
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when(underflow || overflow){
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done := True
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val low = overflow
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val high = input.arg(0) ^ overflow
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input.rs1Raw.getDrivingReg(0, 32 bits) := (31 -> high, default -> low)
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} otherwise {
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manTop := (U(exponentOne + 31) - input.rs1.exponent).resized //TODO merge
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input.rs1Raw.getDrivingReg(0, 32 bits) := input.rs1Raw(0, 23 bits) << 9
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}
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shift.by := (U(exponentOne + 31) - input.rs1.exponent).min(U(33)).resized //TODO merge
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} otherwise {
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manTop := (U(exponentOne - 127) - recoded.exponent).resized
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shift.by := (U(exponentOne - 127+10) - recoded.exponent).resized
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}
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boot := False
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} otherwise {
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when(isF2i){
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input.rs1Raw.getDrivingReg(0, 32 bits) := (B(counter === 0 && !isZero) ## input.rs1Raw(0, 32 bits)) >> 1
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} otherwise {
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input.rs1Raw.getDrivingReg(0, 23 bits) := (B(counter === 0) ## input.rs1Raw(0, 23 bits)) >> 1
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}
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counter := counter + 1
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when(counter === manTop) {
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done := True
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}
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done := True
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}
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}
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when(isSubnormal){
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f32.exp := 0
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f32.man := shift.output(22 downto 0)
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}
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when(!input.isStall){
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counter := 0
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done := False
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boot := True
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}
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@ -526,12 +520,30 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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}
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// val f2iShift = input.rs1.exponent - U(exponentOne)
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// val f2iShifted = (U"1" @@ input.rs1.mantissa) << (f2iShift.resize(5 bits))
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// val f2iUnsigned = f2iShifted >> p.internalMantissaSize
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// val f2iResult = (f2iUnsigned.twoComplement(input.arg(0) && input.rs1.sign)).asBits.resize(32 bits)
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val f2iUnsigned = input.rs1Raw(0, 32 bits).asUInt
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val f2iResult = (f2iUnsigned.twoComplement(input.arg(0) && input.rs1.sign)).asBits.resize(32 bits)
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val f2i = new Area{ //Will not work for 64 bits float max value rounding
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val unsigned = fsm.shift.output >> 1
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val resign = input.arg(0) && input.rs1.sign
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val round = fsm.shift.output(0) ## fsm.shift.scrap
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val increment = input.roundMode.mux(
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FpuRoundMode.RNE -> (round(1) && (round(0) || unsigned(0))),
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FpuRoundMode.RTZ -> False,
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FpuRoundMode.RDN -> (round =/= 0 && input.rs1.sign),
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FpuRoundMode.RUP -> (round =/= 0 && !input.rs1.sign),
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FpuRoundMode.RMM -> (round(1))
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)
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val result = (Mux(resign, ~unsigned, unsigned) + (resign ^ increment).asUInt)
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val overflow = RegNext((input.rs1.exponent > (input.arg(0) ? U(exponentOne+30) | U(exponentOne+31)) || input.rs1.isInfinity) && !input.rs1.sign || input.rs1.isNan)
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val underflow = RegNext((input.rs1.exponent > U(exponentOne+30) || !input.arg(0) || input.rs1.isInfinity) && input.rs1.sign)
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val isZero = input.rs1.isZero
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when(isZero){
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result := 0
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} elsewhen(underflow || overflow) {
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val low = overflow
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val high = input.arg(0) ^ overflow
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result := (31 -> high, default -> low)
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}
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}
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val bothZero = input.rs1.isZero && input.rs2.isZero
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val rs1Equal = input.rs1 === input.rs2
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@ -569,7 +581,7 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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switch(input.opcode){
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is(FpuOpcode.STORE) { result := recodedResult }
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is(FpuOpcode.FMV_X_W) { result := recodedResult } //TODO
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is(FpuOpcode.F2I) { result := f2iResult }
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is(FpuOpcode.F2I) { result := f2i.result.asBits }
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is(FpuOpcode.CMP) { result := cmpResult.resized } //TODO
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is(FpuOpcode.FCLASS) { result := fclassResult.resized }
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}
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@ -1057,6 +1069,13 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
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port.address := input.source @@ input.rd
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port.data := input.value
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if(p.sim) when(port.data.isZero || port.data.isInfinity){
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port.data.mantissa.assignDontCare()
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}
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if(p.sim) when(port.data.special){
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port.data.exponent(p.internalExponentSize-1 downto 2).assignDontCare()
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}
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when(port.valid){
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assert(!(port.data.exponent === 0 && !port.data.special), "Special violation")
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assert(!(port.data.exponent === port.data.exponent.maxValue && !port.data.special), "Special violation")
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@ -106,7 +106,8 @@ object FpuRoundModeInstr extends SpinalEnum(){
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case class FpuParameter( internalMantissaSize : Int,
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withDouble : Boolean){
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withDouble : Boolean,
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sim : Boolean = false){
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val storeLoadType = HardType(Bits(if(withDouble) 64 bits else 32 bits))
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val internalExponentSize = (if(withDouble) 11 else 8) + 1
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@ -32,7 +32,8 @@ class FpuTest extends FunSuite{
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val portCount = 1
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val p = FpuParameter(
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internalMantissaSize = 23,
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withDouble = false
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withDouble = false,
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sim = true
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)
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val config = SimConfig
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@ -46,16 +47,19 @@ class FpuTest extends FunSuite{
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class TestCase(op : String){
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def build(arg : String) = new ProcessStream(s"testfloat_gen $arg -forever -$op"){
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def f32_2 ={
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val l = next
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val s = new Scanner(l)
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val s = new Scanner(next)
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(b2f(s.nextLong(16).toInt), b2f(s.nextLong(16).toInt), b2f(s.nextLong(16).toInt), s.nextInt(16))
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}
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def i32_f32 ={
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val l = next
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val s = new Scanner(l)
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val s = new Scanner(next)
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(s.nextLong(16).toInt, b2f(s.nextLong(16).toInt), s.nextInt(16))
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}
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def f32_i32 = {
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val s = new Scanner(next)
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(b2f(s.nextLong(16).toInt), s.nextLong(16).toInt, s.nextInt(16))
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}
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}
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val RNE = build("-rnear_even")
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val RTZ = build("-rminMag")
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@ -75,10 +79,12 @@ class FpuTest extends FunSuite{
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val f32 = new {
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val add = new TestCase("f32_add")
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val sub = new TestCase("f32_sub")
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val mul = new TestCase("f32_mul")
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val ui2f = new TestCase("ui32_to_f32")
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val i2f = new TestCase("i32_to_f32")
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val f2ui = new TestCase("f32_to_ui32")
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val f2i = new TestCase("f32_to_i32")
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}
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val cpus = for(id <- 0 until portCount) yield new {
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@ -147,14 +153,14 @@ class FpuTest extends FunSuite{
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storeRaw(rs){rsp => body(b2f(rsp.value.toLong.toInt))}
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}
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def mul(rd : Int, rs1 : Int, rs2 : Int, rounding : FpuRoundMode.E = FpuRoundMode.RNE): Unit ={
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def fpuF2f(rd : Int, rs1 : Int, rs2 : Int, rs3 : Int, opcode : FpuOpcode.E, arg : Int, rounding : FpuRoundMode.E = FpuRoundMode.RNE): Unit ={
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cmdQueue += {cmd =>
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cmd.opcode #= cmd.opcode.spinalEnum.MUL
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cmd.opcode #= opcode
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cmd.rs1 #= rs1
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cmd.rs2 #= rs2
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cmd.rs3.randomize()
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cmd.rd #= rd
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cmd.arg #= 0
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cmd.arg #= arg
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cmd.roundMode #= rounding
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}
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commitQueue += {cmd =>
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@ -163,90 +169,51 @@ class FpuTest extends FunSuite{
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}
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}
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def fpuF2i(rs1 : Int, rs2 : Int, opcode : FpuOpcode.E, arg : Int, rounding : FpuRoundMode.E = FpuRoundMode.RNE)(body : FpuRsp => Unit): Unit ={
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cmdQueue += {cmd =>
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cmd.opcode #= opcode
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cmd.rs1 #= rs1
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cmd.rs2 #= rs2
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cmd.rs3.randomize()
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cmd.rd.randomize()
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cmd.arg #= arg
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cmd.roundMode #= rounding
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}
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rspQueue += body
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}
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def mul(rd : Int, rs1 : Int, rs2 : Int, rounding : FpuRoundMode.E = FpuRoundMode.RNE): Unit ={
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fpuF2f(rd, rs1, rs2, Random.nextInt(32), FpuOpcode.MUL, 0, rounding)
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}
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def add(rd : Int, rs1 : Int, rs2 : Int, rounding : FpuRoundMode.E = FpuRoundMode.RNE): Unit ={
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cmdQueue += {cmd =>
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cmd.opcode #= cmd.opcode.spinalEnum.ADD
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cmd.rs1 #= rs1
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cmd.rs2 #= rs2
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cmd.rs3.randomize()
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cmd.rd #= rd
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cmd.arg #= 0
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cmd.roundMode #= rounding
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}
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commitQueue += {cmd =>
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cmd.write #= true
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cmd.sync #= false
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}
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fpuF2f(rd, rs1, rs2, Random.nextInt(32), FpuOpcode.ADD, 0, rounding)
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}
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def div(rd : Int, rs1 : Int, rs2 : Int): Unit ={
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cmdQueue += {cmd =>
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cmd.opcode #= cmd.opcode.spinalEnum.DIV
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cmd.rs1 #= rs1
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cmd.rs2 #= rs2
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cmd.rs3.randomize()
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cmd.rd #= rd
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cmd.arg.randomize()
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}
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commitQueue += {cmd =>
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cmd.write #= true
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cmd.sync #= false
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}
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def sub(rd : Int, rs1 : Int, rs2 : Int, rounding : FpuRoundMode.E = FpuRoundMode.RNE): Unit ={
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fpuF2f(rd, rs1, rs2, Random.nextInt(32), FpuOpcode.ADD, 1, rounding)
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}
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def sqrt(rd : Int, rs1 : Int): Unit ={
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cmdQueue += {cmd =>
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cmd.opcode #= cmd.opcode.spinalEnum.SQRT
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cmd.rs1 #= rs1
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cmd.rs2.randomize()
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cmd.rs3.randomize()
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cmd.rd #= rd
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cmd.arg.randomize()
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}
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commitQueue += {cmd =>
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cmd.write #= true
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cmd.sync #= false
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}
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def div(rd : Int, rs1 : Int, rs2 : Int, rounding : FpuRoundMode.E = FpuRoundMode.RNE): Unit ={
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fpuF2f(rd, rs1, rs2, Random.nextInt(32), FpuOpcode.DIV, Random.nextInt(4), rounding)
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}
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def fma(rd : Int, rs1 : Int, rs2 : Int, rs3 : Int): Unit ={
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cmdQueue += {cmd =>
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cmd.opcode #= cmd.opcode.spinalEnum.FMA
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cmd.rs1 #= rs1
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cmd.rs2 #= rs2
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cmd.rs3 #= rs3
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cmd.rd #= rd
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cmd.arg #= 0
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}
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commitQueue += {cmd =>
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cmd.write #= true
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cmd.sync #= false
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}
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def sqrt(rd : Int, rs1 : Int, rounding : FpuRoundMode.E = FpuRoundMode.RNE): Unit ={
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fpuF2f(rd, rs1, Random.nextInt(32), Random.nextInt(32), FpuOpcode.SQRT, Random.nextInt(4), rounding)
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}
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def fma(rd : Int, rs1 : Int, rs2 : Int, rs3 : Int, rounding : FpuRoundMode.E = FpuRoundMode.RNE): Unit ={
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fpuF2f(rd, rs1, rs2, rs3, FpuOpcode.FMA, 0, rounding)
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}
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def cmp(rs1 : Int, rs2 : Int)(body : FpuRsp => Unit): Unit ={
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cmdQueue += {cmd =>
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cmd.opcode #= cmd.opcode.spinalEnum.CMP
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cmd.rs1 #= rs1
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cmd.rs2 #= rs2
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cmd.rs3.randomize()
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cmd.rd.randomize()
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cmd.arg #= 1
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}
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rspQueue += body
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fpuF2i(rs1, rs2, FpuOpcode.CMP, 1, FpuRoundMode.elements.randomPick())(body)
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}
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def f2i(rs1 : Int, signed : Boolean)(body : FpuRsp => Unit): Unit ={
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cmdQueue += {cmd =>
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cmd.opcode #= cmd.opcode.spinalEnum.F2I
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cmd.rs1 #= rs1
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cmd.rs2.randomize()
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cmd.rs3.randomize()
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cmd.rd.randomize()
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cmd.arg #= (if(signed) 1 else 0)
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}
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rspQueue += body
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def f2i(rs1 : Int, signed : Boolean, rounding : FpuRoundMode.E = FpuRoundMode.RNE)(body : FpuRsp => Unit): Unit ={
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fpuF2i(rs1, Random.nextInt(32), FpuOpcode.F2I, if(signed) 1 else 0, rounding)(body)
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}
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def i2f(rd : Int, value : Int, signed : Boolean, rounding : FpuRoundMode.E = FpuRoundMode.RNE): Unit ={
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@ -388,6 +355,18 @@ class FpuTest extends FunSuite{
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}
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}
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def testBinaryOp(op : (Int,Int,Int,FpuRoundMode.E) => Unit, a : Float, b : Float, ref : Float, flag : Int, rounding : FpuRoundMode.E, opName : String): Unit ={
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val rs = new RegAllocator()
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val rs1, rs2, rs3 = rs.allocate()
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val rd = Random.nextInt(32)
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load(rs1, a)
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load(rs2, b)
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op(rd,rs1,rs2, rounding)
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storeFloat(rd){v =>
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assert(f2b(v) == f2b(ref), f"## ${a} ${opName} $b = $v, $ref $rounding")
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}
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}
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def testAddExact(a : Float, b : Float, ref : Float, flag : Int, rounding : FpuRoundMode.E): Unit ={
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val rs = new RegAllocator()
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val rs1, rs2, rs3 = rs.allocate()
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@ -517,6 +496,31 @@ class FpuTest extends FunSuite{
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}
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}
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def testF2iExact(a : Float, ref : Int, flag : Int, signed : Boolean, rounding : FpuRoundMode.E): Unit ={
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val rs = new RegAllocator()
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val rs1 = rs.allocate()
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val rd = Random.nextInt(32)
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load(rs1, a)
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f2i(rs1, signed, rounding){rsp =>
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if(signed) {
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val v = rsp.value.toLong.toInt
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var ref2 = ref
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if(a >= Int.MaxValue) ref2 = Int.MaxValue
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||||
if(a <= Int.MinValue) ref2 = Int.MinValue
|
||||
if(a.isNaN) ref2 = Int.MaxValue
|
||||
assert(v == (ref2), f" <= f2i($a) = $v, $ref2, $rounding, $flag")
|
||||
} else {
|
||||
val v = rsp.value.toLong
|
||||
var ref2 = ref.toLong & 0xFFFFFFFFl
|
||||
if(a < 0) ref2 = 0
|
||||
if(a >= 0xFFFFFFFFl) ref2 = 0xFFFFFFFFl
|
||||
if(a.isNaN) ref2 = 0xFFFFFFFFl
|
||||
assert(v == ref2, f" <= f2ui($a) = $v, $ref2, $rounding $flag")
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
def testI2f(a : Int, signed : Boolean): Unit ={
|
||||
val rs = new RegAllocator()
|
||||
val rd = Random.nextInt(32)
|
||||
|
|
@ -538,7 +542,7 @@ class FpuTest extends FunSuite{
|
|||
val aLong = if(signed) a.toLong else a.toLong & 0xFFFFFFFFl
|
||||
val ref = b
|
||||
// println(f"i2f($aLong) = $v, $ref")
|
||||
assert(f2b(v) == f2b(ref))
|
||||
assert(f2b(v) == f2b(ref), f"i2f($aLong) = $v, $ref")
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -647,6 +651,7 @@ class FpuTest extends FunSuite{
|
|||
}
|
||||
|
||||
|
||||
|
||||
// for(i <- 0 until 64){
|
||||
// val rounding = FpuRoundMode.RMM
|
||||
// val a = 24f
|
||||
|
|
@ -656,36 +661,63 @@ class FpuTest extends FunSuite{
|
|||
// testMulExact(a,b,c,f, rounding)
|
||||
// }
|
||||
|
||||
for(_ <- 0 until 100000){
|
||||
val binaryOps = List[(Int,Int,Int,FpuRoundMode.E) => Unit](add, sub, mul)
|
||||
|
||||
|
||||
|
||||
for(_ <- 0 until 10000){
|
||||
val rounding = FpuRoundMode.elements.randomPick()
|
||||
val (a,b,f) = f32.i2f(rounding).i32_f32
|
||||
testI2fExact(a,b,f, true, rounding)
|
||||
}
|
||||
for(_ <- 0 until 100000){
|
||||
|
||||
for(_ <- 0 until 10000){
|
||||
val rounding = FpuRoundMode.elements.randomPick()
|
||||
val (a,b,f) = f32.ui2f(rounding).i32_f32
|
||||
testI2fExact(a,b,f, false, rounding)
|
||||
}
|
||||
println("i2f done")
|
||||
|
||||
for(_ <- 0 until 10000){
|
||||
val rounding = FpuRoundMode.elements.randomPick()
|
||||
val (a,b,f) = f32.f2ui(rounding).f32_i32
|
||||
testF2iExact(a,b, f, false, rounding)
|
||||
}
|
||||
|
||||
for(_ <- 0 until 100000){
|
||||
for(_ <- 0 until 10000){
|
||||
val rounding = FpuRoundMode.elements.randomPick()
|
||||
val (a,b,f) = f32.f2i(rounding).f32_i32
|
||||
testF2iExact(a,b, f, true, rounding)
|
||||
}
|
||||
|
||||
println("f2i done")
|
||||
|
||||
|
||||
for(_ <- 0 until 10000){
|
||||
val rounding = FpuRoundMode.elements.randomPick()
|
||||
val (a,b,c,f) = f32.add(rounding).f32_2
|
||||
testBinaryOp(add,a,b,c,f, rounding,"add")
|
||||
}
|
||||
|
||||
for(_ <- 0 until 10000){
|
||||
val rounding = FpuRoundMode.elements.randomPick()
|
||||
val (a,b,c,f) = f32.sub(rounding).f32_2
|
||||
testBinaryOp(sub,a,b,c,f, rounding,"sub")
|
||||
}
|
||||
|
||||
println("Add done")
|
||||
|
||||
for(_ <- 0 until 10000){
|
||||
val rounding = FpuRoundMode.elements.randomPick()
|
||||
val (a,b,c,f) = f32.mul(rounding).f32_2
|
||||
testMulExact(a,b,c,f, rounding)
|
||||
testBinaryOp(mul,a,b,c,f, rounding,"mul")
|
||||
}
|
||||
|
||||
println("Mul done")
|
||||
|
||||
|
||||
|
||||
for(_ <- 0 until 100000){
|
||||
val rounding = FpuRoundMode.elements.randomPick()
|
||||
val (a,b,c,f) = f32.add(rounding).f32_2
|
||||
testAddExact(a,b,c,f, rounding)
|
||||
}
|
||||
|
||||
println("Add done")
|
||||
|
||||
waitUntil(cmdQueue.isEmpty)
|
||||
dut.clockDomain.waitSampling(1000)
|
||||
|
|
|
|||
Loading…
Reference in a new issue